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| author | Ashish Chaudhari <ashish@ettus.com> | 2018-02-20 11:42:56 -0800 |
|---|---|---|
| committer | Ashish Chaudhari <ashish.chaudhari@ettus.com> | 2018-02-21 16:50:18 -0800 |
| commit | d5109ae99e5da24707a8d7a6d57b96f6deabbede (patch) | |
| tree | 7f06c5cbb5e820323f083731fac0d2477e04c06c | |
| parent | cf644768c43cc15844e3f1b64f6e363634719f5e (diff) | |
| download | uhd-d5109ae99e5da24707a8d7a6d57b96f6deabbede.tar.gz uhd-d5109ae99e5da24707a8d7a6d57b96f6deabbede.tar.bz2 uhd-d5109ae99e5da24707a8d7a6d57b96f6deabbede.zip | |
rfnoc,x300: Multiple clocking changes
- Moved bus_clk <=> ce_clk crossing to axi_wrapper in FPGA
which resulted in a noc_shell compat bump
- Change x300 bus_clk frequency to 187.5 MHz
| -rwxr-xr-x | firmware/usrp3/x300/x300_aurora_bist.py | 2 | ||||
| m--------- | fpga-src | 0 | ||||
| -rw-r--r-- | host/include/uhd/rfnoc/constants.hpp | 2 | ||||
| -rw-r--r-- | host/lib/usrp/x300/x300_fw_common.h | 2 | ||||
| -rw-r--r-- | host/lib/usrp/x300/x300_impl.hpp | 6 | ||||
| -rw-r--r-- | images/manifest.txt | 18 |
6 files changed, 15 insertions, 15 deletions
diff --git a/firmware/usrp3/x300/x300_aurora_bist.py b/firmware/usrp3/x300/x300_aurora_bist.py index 5f7a22a3b..962494b46 100755 --- a/firmware/usrp3/x300/x300_aurora_bist.py +++ b/firmware/usrp3/x300/x300_aurora_bist.py @@ -61,7 +61,7 @@ MAC_CTRL_PHY_RESET = 0x00000200 MAC_CTRL_BIST_RATE_MSK = 0x000001F8 MAC_CTRL_BIST_RATE_OFFSET = 3 -BUS_CLK_RATE = 166.66e6 +BUS_CLK_RATE = 187.50e6 BIST_MAX_TIME_LIMIT = math.floor(pow(2,48)/BUS_CLK_RATE)-1 ######################################################################## diff --git a/fpga-src b/fpga-src -Subproject 8570a45339bd35ebb445f7c455f1c80a804f7c0 +Subproject 2824f7b94b12bc8152900243830f7afc105d87e diff --git a/host/include/uhd/rfnoc/constants.hpp b/host/include/uhd/rfnoc/constants.hpp index 05d6864e5..53514c157 100644 --- a/host/include/uhd/rfnoc/constants.hpp +++ b/host/include/uhd/rfnoc/constants.hpp @@ -25,7 +25,7 @@ static const std::string XML_PATH_ENV = "UHD_RFNOC_DIR"; //! If the block name can't be automatically detected, this name is used static const std::string DEFAULT_BLOCK_NAME = "Block"; static const uint64_t DEFAULT_NOC_ID = 0xFFFFFFFFFFFFFFFF; -static const size_t NOC_SHELL_COMPAT_MAJOR = 1; +static const size_t NOC_SHELL_COMPAT_MAJOR = 2; static const size_t NOC_SHELL_COMPAT_MINOR = 0; static const size_t MAX_PACKET_SIZE = 8000; // bytes diff --git a/host/lib/usrp/x300/x300_fw_common.h b/host/lib/usrp/x300/x300_fw_common.h index 67a1e16fa..9cfae8e16 100644 --- a/host/lib/usrp/x300/x300_fw_common.h +++ b/host/lib/usrp/x300/x300_fw_common.h @@ -23,7 +23,7 @@ extern "C" { #define X300_REVISION_MIN 2 #define X300_FW_COMPAT_MAJOR 5 #define X300_FW_COMPAT_MINOR 2 -#define X300_FPGA_COMPAT_MAJOR 0x22 +#define X300_FPGA_COMPAT_MAJOR 0x23 //shared memory sections - in between the stack and the program space #define X300_FW_SHMEM_BASE 0x6000 diff --git a/host/lib/usrp/x300/x300_impl.hpp b/host/lib/usrp/x300/x300_impl.hpp index f5c445d3a..9e89ca542 100644 --- a/host/lib/usrp/x300/x300_impl.hpp +++ b/host/lib/usrp/x300/x300_impl.hpp @@ -34,9 +34,9 @@ static const std::string X300_FW_FILE_NAME = "usrp_x300_fw.bin"; static const std::string X300_DEFAULT_CLOCK_SOURCE = "internal"; -static const double X300_DEFAULT_TICK_RATE = 200e6; //Hz -static const double X300_DEFAULT_DBOARD_CLK_RATE = 50e6; //Hz -static const double X300_BUS_CLOCK_RATE = 166.666667e6; //Hz +static const double X300_DEFAULT_TICK_RATE = 200e6; //Hz +static const double X300_DEFAULT_DBOARD_CLK_RATE = 50e6; //Hz +static const double X300_BUS_CLOCK_RATE = 187.5e6; //Hz static const size_t X300_RX_SW_BUFF_SIZE_ETH = 0x2000000;//32MiB For an ~8k frame size any size >32MiB is just wasted buffer space static const size_t X300_RX_SW_BUFF_SIZE_ETH_MACOS = 0x100000; //1Mib diff --git a/images/manifest.txt b/images/manifest.txt index 8ed7ef6b5..f0a9fdcc0 100644 --- a/images/manifest.txt +++ b/images/manifest.txt @@ -1,15 +1,15 @@ # UHD Image Manifest File # Target hash url SHA256 # X300-Series -x3xx_x310_fpga_default fpga-30cc152 x3xx/fpga-30cc152/x3xx_x310_fpga_default.zip 0a7a410013ab83efca8101defc7bcb5346e74a03b6412e8d9077b3b5728b93f5 -x3xx_x300_fpga_default fpga-30cc152 x3xx/fpga-30cc152/x3xx_x300_fpga_default.zip c4814bc948a1ce06ccc85ed6c58c4946e12a150a27ce3fc94080f7ff98669f2f +x3xx_x310_fpga_default fpga-1c568e6 x3xx/fpga-1c568e6/x3xx_x310_fpga_default.zip d441d1b51c2b4f12fd83b09b0d1937265f8b537dfb98f5a0e7bfe611a53abb7e +x3xx_x300_fpga_default fpga-1c568e6 x3xx/fpga-1c568e6/x3xx_x300_fpga_default.zip e2413b6690029481991155d79e760d2e68a443df0e7cb95672083737424837db # Example daughterboard targets (none currently exist) #x3xx_twinrx_cpld_default example_target #dboard_ubx_cpld_default example_target # E-Series -e3xx_e310_fpga_default fpga-30cc152 e3xx/fpga-30cc152/e3xx_e310_fpga_default.zip c2c996190be6c4ada2e176a0e2b647dfe7a56100cc3c140ca5bc702411747530 +e3xx_e310_fpga_default fpga-1c568e6 e3xx/fpga-1c568e6/e3xx_e310_fpga_default.zip 2957b4bdefe6885644ef2bc7b0e3845d13a7fe45f5a0933a2adaffd24c1b6802 # N300-Series -n3xx_n310_fpga_default fpga-8570a45 n3xx/fpga-8570a45/n3xx_n310_fpga_default.zip 3e53a28ccf8cf01128e8f05e7741fa68beccd9b7b50abddd6c06a4d7f8bd6fd9 +n3xx_n310_fpga_default fpga-1c568e6 n3xx/fpga-1c568e6/n3xx_n310_fpga_default.zip 658bc41282107940a22f19f95581cfe7007642fdfde5a1261c0e92c741782120 n3xx_n310_fpga_aurora fpga-6bea23d n3xx/fpga-6bea23d/n3xx_n310_fpga_aurora.zip 62a12a2c85526f759c96a1eb7db226e715cdd83b9c277d29f037ae00c72bf7fa #n3xx_n310_cpld_default fpga-6bea23d n3xx/fpga-6bea23d/n3xx_n310_cpld_default.zip 0 # N3XX Mykonos firmware @@ -21,10 +21,10 @@ n3xx_n310_fpga_aurora fpga-6bea23d n3xx/fpga-6bea23d/n3xx_n310_ #n3xx_n310_sdimg_default fpga-6bea23d n3xx/fpga-6bea23d/n3xx_n310_sdimg_default.zip 0 #n3xx_n300_sdimg_default fpga-6bea23d n3xx/fpga-6bea23d/n3xx_n300_sdimg_default.zip 0 # B200-Series -b2xx_b200_fpga_default fpga-6bea23d b2xx/fpga-6bea23d/b2xx_b200_fpga_default.zip f7d0a3d33e026484d89c420df66fe3a698717126f8407ef02240b323d4a12839 -b2xx_b200mini_fpga_default fpga-6bea23d b2xx/fpga-6bea23d/b2xx_b200mini_fpga_default.zip 7fa95b938f0bfbdce821c23950d28ca43e7ef24a7cda39a0b2f09fac84f24aae -b2xx_b210_fpga_default fpga-6bea23d b2xx/fpga-6bea23d/b2xx_b210_fpga_default.zip e08dbdaa6508c1fd480463f40231ef3b221b6f78567fab7db72c1d367d396c6f -b2xx_b205mini_fpga_default fpga-6bea23d b2xx/fpga-6bea23d/b2xx_b205mini_fpga_default.zip a74598cd9ecc71f34e8fba06b31c303d0f1a88532e9689efaff516aa6d5e1ff6 +b2xx_b200_fpga_default fpga-1c568e6 b2xx/fpga-1c568e6/b2xx_b200_fpga_default.zip 7ba7561d517dc9a474b01f06c273f921a3a27005e41cd38fde7cd03bbb00284f +b2xx_b200mini_fpga_default fpga-1c568e6 b2xx/fpga-1c568e6/b2xx_b200mini_fpga_default.zip 5cf63ec2d50630c35b6614729ae426d209cda48b02f25dd6eb31650f6ffe5bab +b2xx_b210_fpga_default fpga-1c568e6 b2xx/fpga-1c568e6/b2xx_b210_fpga_default.zip 612b239f86a6d1b09736c6eb55cfe370937d0414acfee48f96cecfe94c080a89 +b2xx_b205mini_fpga_default fpga-1c568e6 b2xx/fpga-1c568e6/b2xx_b205mini_fpga_default.zip ab4de1ff063cb2224f74f17c6e7371fec314cb95fcef2a8035529a3fe1e6355f b2xx_common_fw_default uhd-14000041 b2xx/uhd-14000041/b2xx_common_fw_default.zip 920790744085d8525529c1d0ece8942fef6d29b0a503530a814727fbacd7732c # USRP2 Devices usrp2_usrp2_fw_default fpga-6bea23d usrp2/fpga-6bea23d/usrp2_usrp2_fw_default.zip d523a18318cb6a7637be40484bf03a6f54766410fee2c1a1f72e8971ea9a9cb6 @@ -33,7 +33,7 @@ usrp2_n200_fpga_default fpga-6bea23d usrp2/fpga-6bea23d/usrp2_n20 usrp2_n200_fw_default fpga-6bea23d usrp2/fpga-6bea23d/usrp2_n200_fw_default.zip 3eee2a6195caafe814912167fccf2dfc369f706446f8ecee36e97d2c0830116f usrp2_n210_fpga_default fpga-6bea23d usrp2/fpga-6bea23d/usrp2_n210_fpga_default.zip 5ce68ac539ee6eeb7d04fb3127c1fabcaff442a8edfaaa2f3746590f9df909bd usrp2_n210_fw_default fpga-6bea23d usrp2/fpga-6bea23d/usrp2_n210_fw_default.zip 3646fcd3fc974d18c621cb10dfe97c4dad6d282036dc63b7379995dfad95fb98 -n230_n230_fpga_default fpga-30cc152 n230/fpga-30cc152/n230_n230_fpga_default.zip 2027230401449bdfa9753ee41121d8b5e5ba28204a2ef8f8e130492152a18233 +n230_n230_fpga_default fpga-1c568e6 n230/fpga-1c568e6/n230_n230_fpga_default.zip 8cf8b5318aa797d180b8a09b2dc39f25418a5952c11ec65687ceb5542a3a59cb # USRP1 Devices usrp1_usrp1_fpga_default fpga-6bea23d usrp1/fpga-6bea23d/usrp1_usrp1_fpga_default.zip 03bf72868c900dd0853bf48e2ede91058d579829b0e70c021e51b0e282d1d5be usrp1_b100_fpga_default fpga-6bea23d usrp1/fpga-6bea23d/usrp1_b100_fpga_default.zip 7f2306f21e17aa3fae3f966d08c6297d6cf42041974f846ca89f0d633ece8769 |