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| author | Ashish Chaudhari <ashish@ettus.com> | 2015-02-16 09:42:50 -0800 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2015-02-16 09:42:50 -0800 |
| commit | cbe636086be75667d6f26e3b773d48914ac76d43 (patch) | |
| tree | 0c3125b391085b57cee2c80d9ecee6b48a012acc | |
| parent | 8ec775e936b15404b34d34fd08cc5b3b3489055b (diff) | |
| download | uhd-cbe636086be75667d6f26e3b773d48914ac76d43.tar.gz uhd-cbe636086be75667d6f26e3b773d48914ac76d43.tar.bz2 uhd-cbe636086be75667d6f26e3b773d48914ac76d43.zip | |
docs: Changed ISE version for usrp3 devices to 14.7
| -rw-r--r-- | host/docs/images.dox | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/host/docs/images.dox b/host/docs/images.dox index bd2ffacf6..1ff9fa7c3 100644 --- a/host/docs/images.dox +++ b/host/docs/images.dox @@ -85,7 +85,7 @@ depending on the device. The build requires that you have a UNIX-like environment with `Make`. Make sure that `xtclsh` from the Xilinx ISE bin directory is in your `$PATH`. -- Xilinx ISE 14.4: USRP X3x0 Series, USRP B2x0 +- Xilinx ISE 14.7: USRP X3x0 Series, USRP B2x0 See `<uhd-repo-path>/fpga/usrp3/top/`. |