ettus.com ip axi_bitq 1.0 S_AXI AWADDR S_AXI_AWADDR AWVALID S_AXI_AWVALID AWREADY S_AXI_AWREADY WDATA S_AXI_WDATA WSTRB S_AXI_WSTRB WVALID S_AXI_WVALID WREADY S_AXI_WREADY BRESP S_AXI_BRESP BVALID S_AXI_BVALID BREADY S_AXI_BREADY ARADDR S_AXI_ARADDR ARVALID S_AXI_ARVALID ARREADY S_AXI_ARREADY RDATA S_AXI_RDATA RRESP S_AXI_RRESP RVALID S_AXI_RVALID RREADY S_AXI_RREADY S_AXI_ARESETN RST S_AXI_ARESETN POLARITY ACTIVE_LOW S_AXI_ACLK CLK S_AXI_ACLK ASSOCIATED_BUSIF S_AXI ASSOCIATED_RESET S_AXI_ARESETN S_AXI reg0 0 16 32 register xilinx_anylanguagesynthesis Synthesis :vivado.xilinx.com:synthesis VHDL axi_bitq xilinx_anylanguagesynthesis_view_fileset viewChecksum 7ba7202f xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation VHDL axi_bitq xilinx_anylanguagebehavioralsimulation_view_fileset viewChecksum 7ba7202f xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum f92e9879 xilinx_testbench Test Bench :vivado.xilinx.com:simulation.testbench xilinx_testbench_view_fileset viewChecksum 657bd79f bit_clk inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation bit_in in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation bit_out inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation bit_stb inout std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_ACLK in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_ARESETN in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_AWADDR in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_AWVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_AWREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_WDATA in 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_WSTRB in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_WVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_WREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_BRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_BVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_BREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_ARADDR in 3 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_ARVALID in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 S_AXI_ARREADY out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_RDATA out 31 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_RRESP out 1 0 std_logic_vector xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_RVALID out std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation S_AXI_RREADY in std_logic xilinx_anylanguagesynthesis xilinx_anylanguagebehavioralsimulation 0 choice_list_9d8b0d81 ACTIVE_HIGH ACTIVE_LOW xilinx_anylanguagesynthesis_view_fileset bitq_fsm.vhd vhdlSource axi_bitq.vhd vhdlSource CHECKSUM_7f11f7eb xilinx_anylanguagebehavioralsimulation_view_fileset bitq_fsm.vhd vhdlSource USED_IN_ipstatic axi_bitq.vhd vhdlSource USED_IN_ipstatic xilinx_xpgui_view_fileset xgui/axi_bitq_v1_0.tcl tclSource CHECKSUM_f92e9879 XGUI_VERSION_2 xilinx_testbench_view_fileset test/bitq_fsm_test.vhd vhdlSource axi_bitq_v1_0 Component_Name axi_bitq_v1_0 zynq /EttusResearch axi_bitq_v1_0 1 user.org:user:axi_bitq:1.0 2018-01-17T16:36:23Z usrp3/lib/vivado_ipi/axi_bitq usrp3/lib/vivado_ipi/axi_bitq usrp3/lib/vivado_ipi/axi_bitq 2015.4