xilinx.com project coregen_s6 1.0 fifo_s6_1Kx36_2clk fifo_s6_1Kx36_2clk false true 1022 5 36 1024 false No_Programmable_Empty_Threshold false false Independent_Clocks_Block_RAM false true 1 Active_High 11 false 10 1024 0 true true Active_High Active_High false true false No_Programmable_Full_Threshold false 11 Asynchronous_Reset First_Word_Fall_Through 1023 true false false 1 Active_High false 4 36 1 false coregen_s6 ./ ./tmp/ ./tmp/_cg/ xc6slx75 spartan6 csg484 -3 BusFormatAngleBracketNotRipped Verilog true Other false false false Ngc false Behavioral Verilog false 2012-04-24+06:33 fifo_s6_2Kx36_2clk fifo_s6_2Kx36_2clk false true 2046 5 36 2048 false No_Programmable_Empty_Threshold false false Independent_Clocks_Block_RAM false true 1 Active_High 12 false 11 2048 0 true true Active_High Active_High false true false No_Programmable_Full_Threshold false 12 Asynchronous_Reset First_Word_Fall_Through 2047 true false false 1 Active_High false 4 36 1 false coregen_s6 ./ ./tmp/ ./tmp/_cg/ xc6slx75 spartan6 csg484 -3 BusFormatAngleBracketNotRipped Verilog true Other false false false Ngc false Behavioral Verilog false 2012-04-24+06:33 fifo_s6_512x36_2clk fifo_s6_512x36_2clk false true 510 5 36 512 false No_Programmable_Empty_Threshold false false Independent_Clocks_Block_RAM false true 1 Active_High 10 false 9 512 0 true true Active_High Active_High false true false No_Programmable_Full_Threshold false 10 Asynchronous_Reset First_Word_Fall_Through 511 true false false 1 Active_High false 4 36 1 false coregen_s6 ./ ./tmp/ ./tmp/_cg/ xc6slx75 spartan6 csg484 -3 BusFormatAngleBracketNotRipped Verilog true Other false false false Ngc false Behavioral Verilog false 2012-04-24+06:33 fifo_xlnx_16x19_2clk fifo_xlnx_16x19_2clk false true 14 5 19 16 false No_Programmable_Empty_Threshold false false Independent_Clocks_Distributed_RAM false true 1 Active_High 5 5 16 0 true Active_High Active_High false true false No_Programmable_Full_Threshold 5 Asynchronous_Reset First_Word_Fall_Through 15 true false false 1 Active_High false 4 19 1 false coregen_s6 ./ ./tmp/ ./tmp/_cg/ xc3s2000 spartan3 fg456 -5 BusFormatAngleBracketNotRipped Verilog false Other false false false Ngc false Behavioral Verilog false 2012-04-24+06:33 fifo_xlnx_16x40_2clk fifo_xlnx_16x40_2clk false false 14 5 40 16 false No_Programmable_Empty_Threshold false false Independent_Clocks_Distributed_RAM false false 1 Active_High 4 4 16 0 true Active_High Active_High false false false No_Programmable_Full_Threshold 4 Asynchronous_Reset First_Word_Fall_Through 15 true false false 1 Active_High false 4 40 1 false coregen_s6 ./ ./tmp/ ./tmp/_cg/ xc3s2000 spartan3 fg456 -5 BusFormatAngleBracketNotRipped Verilog false Other false false false Ngc false Behavioral Verilog false 2012-04-24+06:33 fifo_xlnx_2Kx36_2clk fifo_xlnx_2Kx36_2clk false true 2046 5 36 2048 false No_Programmable_Empty_Threshold false false Independent_Clocks_Block_RAM false true 1 Active_High 12 12 2048 0 true Active_High Active_High false true false No_Programmable_Full_Threshold 12 Asynchronous_Reset First_Word_Fall_Through 2047 true false false 1 Active_High false 4 36 1 false coregen_s6 ./ ./tmp/ ./tmp/_cg/ xc3s2000 spartan3 fg456 -5 BusFormatAngleBracketNotRipped VHDL true Foundation_ISE false false false Ngc false Behavioral VHDL_and_Verilog false 2012-04-24+06:33 fifo_xlnx_32x36_2clk fifo_xlnx_32x36_2clk false false 23 5 36 32 false No_Programmable_Empty_Threshold false false Independent_Clocks_Distributed_RAM false false 1 Active_High 5 false 5 32 0 true true Active_High Active_High false false false Single_Programmable_Full_Threshold_Constant false 5 Asynchronous_Reset First_Word_Fall_Through 24 true true false 1 Active_High false 4 36 1 false coregen_s6 ./ ./tmp/ ./tmp/_cg/ xc3s2000 spartan3 fg456 -5 BusFormatAngleBracketNotRipped Verilog false Other false false false Ngc false Structural Verilog false 2012-04-24+06:33 fifo_xlnx_512x36_2clk fifo_xlnx_512x36_2clk false true 510 5 36 512 false No_Programmable_Empty_Threshold false false Independent_Clocks_Block_RAM false true 1 Active_High 10 10 512 0 true Active_High Active_High false true false No_Programmable_Full_Threshold 10 Asynchronous_Reset First_Word_Fall_Through 511 true false false 1 Active_High false 4 36 1 false coregen_s6 ./ ./tmp/ ./tmp/_cg/ xc3s2000 spartan3 fg456 -5 BusFormatAngleBracketNotRipped Verilog false Other false false false Ngc false Behavioral Verilog false 2012-04-24+06:33 fifo_xlnx_512x36_2clk_18to36 fifo_xlnx_512x36_2clk_18to36 false false 1014 5 36 1024 false No_Programmable_Empty_Threshold false false Independent_Clocks_Block_RAM false false 0 Active_High 10 false 10 512 0 true true Active_High Active_High false false false Single_Programmable_Full_Threshold_Constant false 9 Asynchronous_Reset First_Word_Fall_Through 1015 true true false 1 Active_High false 4 18 1 false coregen_s6 ./ ./tmp/ ./tmp/_cg/ xc3s2000 spartan3 fg456 -5 BusFormatAngleBracketNotRipped Verilog false Other false false false Ngc false Behavioral Verilog false 2012-04-24+06:33 fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18 false false 508 5 18 512 false No_Programmable_Empty_Threshold false false Independent_Clocks_Block_RAM false false 0 Active_High 9 false 9 1024 0 true true Active_High Active_High false false false No_Programmable_Full_Threshold false 10 Asynchronous_Reset First_Word_Fall_Through 509 true false false 1 Active_High false 4 36 1 false coregen_s6 ./ ./tmp/ ./tmp/_cg/ xc3s2000 spartan3 fg456 -5 BusFormatAngleBracketNotRipped Verilog false Other false false false Ngc false Behavioral Verilog false 2012-04-24+06:33 fifo_xlnx_512x36_2clk_prog_full fifo_xlnx_512x36_2clk_prog_full false false 499 5 36 512 false No_Programmable_Empty_Threshold false false Independent_Clocks_Block_RAM false false 1 Active_High 9 false 9 512 0 true true Active_High Active_High false false false Single_Programmable_Full_Threshold_Constant false 9 Asynchronous_Reset First_Word_Fall_Through 500 true true false 1 Active_High false 4 36 1 false coregen_s6 ./ ./tmp/ ./tmp/_cg/ xc3s2000 spartan3 fg456 -5 BusFormatAngleBracketNotRipped Verilog false Other false false false Ngc false Behavioral Verilog false 2012-04-24+06:33 fifo_xlnx_64x36_2clk fifo_xlnx_64x36_2clk false true 62 5 36 64 false No_Programmable_Empty_Threshold false false Independent_Clocks_Distributed_RAM false true 1 Active_High 7 7 64 0 true Active_High Active_High false true false No_Programmable_Full_Threshold 7 Asynchronous_Reset First_Word_Fall_Through 63 true false false 1 Active_High false 4 36 1 false coregen_s6 ./ ./tmp/ ./tmp/_cg/ xc3s2000 spartan3 fg456 -5 BusFormatAngleBracketNotRipped Verilog false Other false false false Ngc false Behavioral Verilog false 2012-04-24+06:33 pll_100_40_75 pll_100_40_75 true true false false false No_Jitter false 40.000 Units_MHz Units_UI REL_PRIMARY 100.000 UI 0.010 0.010 0.010 0.010 250.0 100.0 true true false false false false 3 false false false false false false false CLK_IN1 CLK_OUT1 CLK_OUT2 CLK_OUT3 CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 DADDR DCLK DRDY DWE DIN DOUT DEN PSCLK PSEN PSINCDEC PSDONE 100.000 0.000 50.0 40.000 0.000 50.0 75.000 0.000 50.0 75.000 0.000 50.0 100.000 0.000 50.0 100.000 0.000 50.0 100.000 0.000 50.0 false false Single_ended_clock_capable_pin false CLK_IN2 Single_ended_clock_capable_pin BUFG BUFG BUFG BUFG BUFG BUFG BUFG FDBK_AUTO SINGLE CLKFB_IN CLKFB_IN_P CLKFB_IN_N CLKFB_OUT CLKFB_OUT_P CLKFB_OUT_N lin empty true DONE true false false false false false false RESET LOCKED POWER_DOWN CLK_VALID STATUS CLK_IN_SEL INPUT_CLK_STOPPED CLKFB_STOPPED false None 1 OPTIMIZED 4.000 0.000 false 10.000 10.000 false false ZHOLD 0.010 0.010 false 4.000 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false None 2.0 2 5 false 25.000 NONE SYSTEM_SYNCHRONOUS 0 1X false CLKFX CLK0 CLKFX CLKFX CLK0 CLK0 false None 1 4 2 0.000 false 10.000 NONE CLKFX CLKFX CLKFX false None OPTIMIZED 15 0.000 CLKFBOUT 1 25.000 SYSTEM_SYNCHRONOUS 0.010 6 0.500 0.000 15 0.500 0.000 8 0.500 0.000 8 0.500 0.000 1 0.500 0.000 1 0.500 0.000 NONE AUTO DCM_SP MMCM 1 1 0 0 0 0 pll_100_40_75 lin 1 1 0.010 0.010 No_Jitter 0 0 0 0 0 0 0 PLL_BASE 0 40.000 Units_MHz 100.000 FDBK_AUTO Single_ended_clock_capable_pin Single_ended_clock_capable_pin SINGLE 1 1 0 0 0 0 0 3 BUFG BUFG BUFG BUFG BUFG BUFG BUFG __primary__________40.000____________0.010 no_secondary_input_clock CLK_OUT1___100.000______0.000______50.0______252.791____220.216 CLK_OUT2____40.000______0.000______50.0______309.264____220.216 CLK_OUT3____75.000______0.000______50.0______269.846____220.216 no_CLK_OUT4_output no_CLK_OUT5_output no_CLK_OUT6_output no_CLK_OUT7_output 100.000 40.000 75.000 75.000 100.000 100.000 100.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 50.0 50.0 50.0 50.0 50.0 50.0 50.0 100.000 40.000 75.000 N/A N/A N/A N/A 0.000 0.000 0.000 N/A N/A N/A N/A 50.0 50.0 50.0 N/A N/A N/A N/A None OPTIMIZED 4.000 10.000 10.000 FALSE FALSE ZHOLD 1 0.010 0.010 FALSE 4.000 1 1 1 1 1 1 0.500 0.500 0.500 0.500 0.500 0.500 0.500 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE None OPTIMIZED CLKFBOUT 15 25.000 SYSTEM_SYNCHRONOUS 1 0.010 6 15 8 8 1 1 0.500 0.500 0.500 0.500 0.500 0.500 0.000 0.000 0.000 0.000 0.000 0.000 0.000 None 2.000 2 5 FALSE 25.0 NONE 1X CLKOUT2 SYSTEM_SYNCHRONOUS 0 FALSE CLKFX CLK0 CLKFX NONE NONE NONE None 2 1 4 25.0 0.000 NONE FALSE CLKFX CLKFX CLKFX AUTO 0 0 0 0 NONE CLK_IN1 CLK_IN2 CLK_OUT1 CLK_OUT2 CLK_OUT3 CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 RESET LOCKED CLKFB_IN CLKFB_IN_P CLKFB_IN_N CLKFB_OUT CLKFB_OUT_P CLKFB_OUT_N POWER_DOWN DADDR DCLK DRDY DWE DIN DOUT DEN PSCLK PSEN PSINCDEC PSDONE CLK_VALID STATUS CLK_IN_SEL INPUT_CLK_STOPPED CLKFB_STOPPED 250.0 100.0 MMCM coregen_s6 ./ ./tmp/ ./tmp/_cg/ xc6slx75 spartan6 csg484 -3 BusFormatAngleBracketNotRipped Verilog true Other false false false Ngc false Behavioral Verilog false 2011-12-28+09:11 apply_current_project_options_generator customization_generator model_parameter_resolution_generator ip_xco_generator ./pll_100_40_75.xco xco Mon Jun 25 01:21:52 GMT 2012 0x7F9C6649 generationID_4013899584 tcl_flow_generator ./pll_100_40_75/example_design/pll_100_40_75_exdes.ucf ucf Mon Jun 25 01:22:01 GMT 2012 0xB54DEDD1 generationID_4013899584 ./pll_100_40_75/example_design/pll_100_40_75_exdes.v verilog Mon Jun 25 01:21:54 GMT 2012 0xF0E263D1 generationID_4013899584 ./pll_100_40_75/example_design/pll_100_40_75_exdes.xdc ignore xdc Mon Jun 25 01:22:02 GMT 2012 0x8A9C2191 generationID_4013899584 ./pll_100_40_75/implement/implement.bat ignore unknown Mon Jun 25 01:22:01 GMT 2012 0x847BA9AE generationID_4013899584 ./pll_100_40_75/implement/implement.sh ignore unknown Mon Jun 25 01:22:01 GMT 2012 0xEF940814 generationID_4013899584 ./pll_100_40_75/implement/planAhead_ise.bat ignore unknown Mon Jun 25 01:22:00 GMT 2012 0x6966A508 generationID_4013899584 ./pll_100_40_75/implement/planAhead_ise.sh ignore unknown Mon Jun 25 01:22:00 GMT 2012 0x7F8B5943 generationID_4013899584 ./pll_100_40_75/implement/planAhead_ise.tcl ignore tcl Mon Jun 25 01:22:00 GMT 2012 0x6D5DA0FA generationID_4013899584 ./pll_100_40_75/implement/planAhead_rdn.bat ignore unknown Mon Jun 25 01:22:00 GMT 2012 0xB9373CFA generationID_4013899584 ./pll_100_40_75/implement/planAhead_rdn.sh ignore unknown Mon Jun 25 01:22:00 GMT 2012 0xDCE9D96C generationID_4013899584 ./pll_100_40_75/implement/planAhead_rdn.tcl ignore tcl Mon Jun 25 01:22:01 GMT 2012 0x9E6E156D generationID_4013899584 ./pll_100_40_75/implement/xst.prj ignore unknown Mon Jun 25 01:22:02 GMT 2012 0x7EF6AFD3 generationID_4013899584 ./pll_100_40_75/implement/xst.scr ignore unknown Mon Jun 25 01:22:02 GMT 2012 0x7BC1F2CC generationID_4013899584 ./pll_100_40_75/simulation/functional/simcmds.tcl ignore tcl Mon Jun 25 01:21:58 GMT 2012 0x80B0E436 generationID_4013899584 ./pll_100_40_75/simulation/functional/simulate_isim.bat ignore unknown Mon Jun 25 01:21:58 GMT 2012 0x3B0D2786 generationID_4013899584 ./pll_100_40_75/simulation/functional/simulate_isim.sh ignore unknown Mon Jun 25 01:21:58 GMT 2012 0x3479DE2E generationID_4013899584 ./pll_100_40_75/simulation/functional/simulate_mti.bat ignore unknown Mon Jun 25 01:21:56 GMT 2012 0x23E49D4C generationID_4013899584 ./pll_100_40_75/simulation/functional/simulate_mti.do ignore unknown Mon Jun 25 01:21:56 GMT 2012 0x196566F3 generationID_4013899584 ./pll_100_40_75/simulation/functional/simulate_mti.sh ignore unknown Mon Jun 25 01:21:56 GMT 2012 0xA92E962D generationID_4013899584 ./pll_100_40_75/simulation/functional/simulate_ncsim.sh ignore unknown Mon Jun 25 01:21:57 GMT 2012 0x414DA0D8 generationID_4013899584 ./pll_100_40_75/simulation/functional/simulate_vcs.sh ignore unknown Mon Jun 25 01:21:59 GMT 2012 0x040C0268 generationID_4013899584 ./pll_100_40_75/simulation/functional/ucli_commands.key ignore unknown Mon Jun 25 01:21:59 GMT 2012 0x957E258B generationID_4013899584 ./pll_100_40_75/simulation/functional/vcs_session.tcl ignore tcl Mon Jun 25 01:21:59 GMT 2012 0x859D76CE generationID_4013899584 ./pll_100_40_75/simulation/functional/wave.do ignore unknown Mon Jun 25 01:21:57 GMT 2012 0xF6D99A50 generationID_4013899584 ./pll_100_40_75/simulation/functional/wave.sv ignore unknown Mon Jun 25 01:21:58 GMT 2012 0x5BAF49BA generationID_4013899584 ./pll_100_40_75/simulation/pll_100_40_75_tb.v ignore verilog Mon Jun 25 01:21:54 GMT 2012 0x338F9EC4 generationID_4013899584 ./pll_100_40_75/simulation/timing/pll_100_40_75_tb.v ignore verilog Mon Jun 25 01:21:55 GMT 2012 0xF8A7FBD8 generationID_4013899584 ./pll_100_40_75/simulation/timing/sdf_cmd_file ignore unknown Mon Jun 25 01:21:57 GMT 2012 0xE37E41C3 generationID_4013899584 ./pll_100_40_75/simulation/timing/simcmds.tcl ignore tcl Mon Jun 25 01:21:58 GMT 2012 0x59F13085 generationID_4013899584 ./pll_100_40_75/simulation/timing/simulate_isim.sh ignore unknown Mon Jun 25 01:21:58 GMT 2012 0x513F3CD7 generationID_4013899584 ./pll_100_40_75/simulation/timing/simulate_mti.bat ignore unknown Mon Jun 25 01:21:56 GMT 2012 0x6032836B generationID_4013899584 ./pll_100_40_75/simulation/timing/simulate_mti.do ignore unknown Mon Jun 25 01:21:56 GMT 2012 0x8556A6D6 generationID_4013899584 ./pll_100_40_75/simulation/timing/simulate_mti.sh ignore unknown Mon Jun 25 01:21:56 GMT 2012 0xF19800C9 generationID_4013899584 ./pll_100_40_75/simulation/timing/simulate_ncsim.sh ignore unknown Mon Jun 25 01:21:57 GMT 2012 0xEFFEEFB9 generationID_4013899584 ./pll_100_40_75/simulation/timing/simulate_vcs.sh ignore unknown Mon Jun 25 01:21:59 GMT 2012 0xE87CCB6C generationID_4013899584 ./pll_100_40_75/simulation/timing/ucli_commands.key ignore unknown Mon Jun 25 01:21:59 GMT 2012 0x9DC0E037 generationID_4013899584 ./pll_100_40_75/simulation/timing/vcs_session.tcl ignore tcl Mon Jun 25 01:22:00 GMT 2012 0x28340249 generationID_4013899584 ./pll_100_40_75/simulation/timing/wave.do ignore unknown Mon Jun 25 01:21:57 GMT 2012 0x251C4591 generationID_4013899584 ./pll_100_40_75.ucf ignore ucf Mon Jun 25 01:22:01 GMT 2012 0x4904DEF4 generationID_4013899584 ./pll_100_40_75.v verilog Mon Jun 25 01:21:53 GMT 2012 0xF7DE77A9 generationID_4013899584 ./pll_100_40_75.veo veo Mon Jun 25 01:21:55 GMT 2012 0xC3431095 generationID_4013899584 ./pll_100_40_75.xdc ignore xdc Mon Jun 25 01:22:01 GMT 2012 0x590C1CA7 generationID_4013899584 ./pll_100_40_75_xmdf.tcl tcl Mon Jun 25 01:21:55 GMT 2012 0x970F3026 generationID_4013899584 associated_files_generator ./pll_100_40_75/clk_wiz_v3_5_readme.txt ignore txt Tue Apr 24 06:24:06 GMT 2012 0x1BF90E4F generationID_4013899584 ejava_generator ./pll_100_40_75/example_design/pll_100_40_75_exdes.ucf ucf Mon Jun 25 01:22:04 GMT 2012 0xB54DEDD1 generationID_4013899584 ./pll_100_40_75/example_design/pll_100_40_75_exdes.v verilog Mon Jun 25 01:22:04 GMT 2012 0xF0E263D1 generationID_4013899584 ./pll_100_40_75/example_design/pll_100_40_75_exdes.xdc ignore xdc Mon Jun 25 01:22:04 GMT 2012 0x8A9C2191 generationID_4013899584 ./pll_100_40_75/implement/implement.bat ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x847BA9AE generationID_4013899584 ./pll_100_40_75/implement/implement.sh ignore unknown Mon Jun 25 01:22:04 GMT 2012 0xEF940814 generationID_4013899584 ./pll_100_40_75/implement/planAhead_ise.bat ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x6966A508 generationID_4013899584 ./pll_100_40_75/implement/planAhead_ise.sh ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x7F8B5943 generationID_4013899584 ./pll_100_40_75/implement/planAhead_ise.tcl ignore tcl Mon Jun 25 01:22:04 GMT 2012 0x6D5DA0FA generationID_4013899584 ./pll_100_40_75/implement/planAhead_rdn.bat ignore unknown Mon Jun 25 01:22:04 GMT 2012 0xB9373CFA generationID_4013899584 ./pll_100_40_75/implement/planAhead_rdn.sh ignore unknown Mon Jun 25 01:22:04 GMT 2012 0xDCE9D96C generationID_4013899584 ./pll_100_40_75/implement/planAhead_rdn.tcl ignore tcl Mon Jun 25 01:22:04 GMT 2012 0x9E6E156D generationID_4013899584 ./pll_100_40_75/implement/xst.prj ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x7EF6AFD3 generationID_4013899584 ./pll_100_40_75/implement/xst.scr ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x7BC1F2CC generationID_4013899584 ./pll_100_40_75/simulation/functional/simcmds.tcl ignore tcl Mon Jun 25 01:22:04 GMT 2012 0x80B0E436 generationID_4013899584 ./pll_100_40_75/simulation/functional/simulate_isim.bat ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x3B0D2786 generationID_4013899584 ./pll_100_40_75/simulation/functional/simulate_isim.sh ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x3479DE2E generationID_4013899584 ./pll_100_40_75/simulation/functional/simulate_mti.bat ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x23E49D4C generationID_4013899584 ./pll_100_40_75/simulation/functional/simulate_mti.do ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x196566F3 generationID_4013899584 ./pll_100_40_75/simulation/functional/simulate_mti.sh ignore unknown Mon Jun 25 01:22:04 GMT 2012 0xA92E962D generationID_4013899584 ./pll_100_40_75/simulation/functional/simulate_ncsim.sh ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x414DA0D8 generationID_4013899584 ./pll_100_40_75/simulation/functional/simulate_vcs.sh ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x040C0268 generationID_4013899584 ./pll_100_40_75/simulation/functional/ucli_commands.key ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x957E258B generationID_4013899584 ./pll_100_40_75/simulation/functional/vcs_session.tcl ignore tcl Mon Jun 25 01:22:04 GMT 2012 0x859D76CE generationID_4013899584 ./pll_100_40_75/simulation/functional/wave.do ignore unknown Mon Jun 25 01:22:04 GMT 2012 0xF6D99A50 generationID_4013899584 ./pll_100_40_75/simulation/functional/wave.sv ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x5BAF49BA generationID_4013899584 ./pll_100_40_75/simulation/pll_100_40_75_tb.v ignore verilog Mon Jun 25 01:22:04 GMT 2012 0x338F9EC4 generationID_4013899584 ./pll_100_40_75/simulation/timing/pll_100_40_75_tb.v ignore verilog Mon Jun 25 01:22:04 GMT 2012 0xF8A7FBD8 generationID_4013899584 ./pll_100_40_75/simulation/timing/sdf_cmd_file ignore unknown Mon Jun 25 01:22:04 GMT 2012 0xE37E41C3 generationID_4013899584 ./pll_100_40_75/simulation/timing/simcmds.tcl ignore tcl Mon Jun 25 01:22:04 GMT 2012 0x59F13085 generationID_4013899584 ./pll_100_40_75/simulation/timing/simulate_isim.sh ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x513F3CD7 generationID_4013899584 ./pll_100_40_75/simulation/timing/simulate_mti.bat ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x6032836B generationID_4013899584 ./pll_100_40_75/simulation/timing/simulate_mti.do ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x8556A6D6 generationID_4013899584 ./pll_100_40_75/simulation/timing/simulate_mti.sh ignore unknown Mon Jun 25 01:22:04 GMT 2012 0xF19800C9 generationID_4013899584 ./pll_100_40_75/simulation/timing/simulate_ncsim.sh ignore unknown Mon Jun 25 01:22:04 GMT 2012 0xEFFEEFB9 generationID_4013899584 ./pll_100_40_75/simulation/timing/simulate_vcs.sh ignore unknown Mon Jun 25 01:22:04 GMT 2012 0xE87CCB6C generationID_4013899584 ./pll_100_40_75/simulation/timing/ucli_commands.key ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x9DC0E037 generationID_4013899584 ./pll_100_40_75/simulation/timing/vcs_session.tcl ignore tcl Mon Jun 25 01:22:04 GMT 2012 0x28340249 generationID_4013899584 ./pll_100_40_75/simulation/timing/wave.do ignore unknown Mon Jun 25 01:22:04 GMT 2012 0x251C4591 generationID_4013899584 ./pll_100_40_75.ucf ignore ucf Mon Jun 25 01:22:04 GMT 2012 0x4904DEF4 generationID_4013899584 ./pll_100_40_75.v verilog Mon Jun 25 01:22:03 GMT 2012 0xF7DE77A9 generationID_4013899584 ./pll_100_40_75.veo veo Mon Jun 25 01:22:04 GMT 2012 0xC3431095 generationID_4013899584 ./pll_100_40_75.xdc ignore xdc Mon Jun 25 01:22:04 GMT 2012 0x590C1CA7 generationID_4013899584 ./pll_100_40_75_xmdf.tcl tcl Mon Jun 25 01:22:04 GMT 2012 0x970F3026 generationID_4013899584 all_documents_generator ./pll_100_40_75/doc/clk_wiz_gsg521.pdf ignore pdf Mon Jun 25 01:22:08 GMT 2012 0x7660EFEE generationID_4013899584 ./pll_100_40_75/doc/clk_wiz_v3_5_readme.txt ignore txt Mon Jun 25 01:22:08 GMT 2012 0x1BF90E4F generationID_4013899584 ./pll_100_40_75/doc/clk_wiz_v3_5_vinfo.html ignore unknown Mon Jun 25 01:22:08 GMT 2012 0xD0135075 generationID_4013899584 readme_documents_generator ./pll_100_40_75/doc/clk_wiz_v3_5_readme.txt ignore txt Mon Jun 25 01:22:09 GMT 2012 0x1BF90E4F generationID_4013899584 asy_generator ./pll_100_40_75.asy asy Mon Jun 25 01:22:17 GMT 2012 0x61F47740 generationID_4013899584 ise_generator ./_xmsgs/pn_parser.xmsgs ignore unknown Mon Jun 25 01:22:24 GMT 2012 0xEDD97934 generationID_4013899584 ./pll_100_40_75.gise ignore gise Mon Jun 25 01:22:25 GMT 2012 0x3AB6E652 generationID_4013899584 ./pll_100_40_75.xise ignore xise Mon Jun 25 01:22:25 GMT 2012 0xAD3860B6 generationID_4013899584 deliver_readme_generator flist_generator ./pll_100_40_75_flist.txt ignore txtFlist txt Mon Jun 25 01:22:25 GMT 2012 0x4D0B8946 generationID_4013899584 view_readme_generator coregen_s6 ./ ./tmp/ ./tmp/_cg/ xc6slx75 spartan6 csg484 -3 BusFormatAngleBracketNotRipped Verilog true Other false false false Ngc false Behavioral Verilog false