From d4649caee02a1c76802dc4f8d7d76bb31b14ce09 Mon Sep 17 00:00:00 2001
From: Matt Ettus <matt@ettus.com>
Date: Tue, 16 Feb 2010 22:49:02 -0800
Subject: wishbone bridge now with minimal functionality.  Need to check timing
 and handle wait states.

---
 usrp2/top/u1e/make.sim | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 usrp2/top/u1e/make.sim

(limited to 'usrp2/top/u1e/make.sim')

diff --git a/usrp2/top/u1e/make.sim b/usrp2/top/u1e/make.sim
new file mode 100644
index 000000000..1c163884c
--- /dev/null
+++ b/usrp2/top/u1e/make.sim
@@ -0,0 +1,7 @@
+all: sim
+
+sim:	
+	iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e
+
+clean:
+	rm -f tb_u1e *.vcd *.lxt a.out
-- 
cgit v1.2.3