From bfff8b79b950f2f1cebfd2db662a4205df5da65a Mon Sep 17 00:00:00 2001 From: Samuel O'Brien Date: Tue, 21 Jul 2020 13:59:39 -0500 Subject: sim: Add Daughterboard Methods This commit adds daughterboard simulation to the simulator. There is a sim_dboard class which registers it's methods with the rpc server. These methods are visible over mpm as well as the mpm_shell. Signed-off-by: Samuel O'Brien --- .../usrp_mpm/simulator/sim_dboard_catalina.py | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 mpm/python/usrp_mpm/simulator/sim_dboard_catalina.py (limited to 'mpm/python/usrp_mpm/simulator/sim_dboard_catalina.py') diff --git a/mpm/python/usrp_mpm/simulator/sim_dboard_catalina.py b/mpm/python/usrp_mpm/simulator/sim_dboard_catalina.py new file mode 100644 index 000000000..4e46d1410 --- /dev/null +++ b/mpm/python/usrp_mpm/simulator/sim_dboard_catalina.py @@ -0,0 +1,33 @@ +# +# Copyright 2020 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: GPL-3.0-or-later +# +from .sim_dboard import SimulatedDboardBase + +class SimulatedCatalinaDboard(SimulatedDboardBase): + pids = [0x0110] + + extra_methods = [ + ("set_gain", lambda target, gain: gain), + ("catalina_tune", lambda which, freq: freq), + ("set_bw_filter", lambda which, freq: freq), + "set_dc_offset_auto", + "set_iq_balance_auto", + "set_agc", + "set_active_chains", + "set_timing_mode", + "data_port_loopback" + ] + + def __init__(self, slot_idx, clock_rate_cb, **kwargs): + super().__init__(slot_idx, **kwargs) + self.clock_rate_cb = clock_rate_cb + self.master_clock_rate = 122.88e6 + + def get_master_clock_rate(self): + return self.master_clock_rate + + def set_catalina_clock_rate(self, rate): + self.clock_rate_cb(rate) + return rate -- cgit v1.2.3