From b5b1ef2de2d554f16f67e254335265186fb642fa Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Wed, 3 May 2017 18:40:31 -0700 Subject: mpm: Various EISCAT fixes --- mpm/python/usrp_mpm/periph_manager/n310.py | 1 + 1 file changed, 1 insertion(+) (limited to 'mpm/python/usrp_mpm/periph_manager/n310.py') diff --git a/mpm/python/usrp_mpm/periph_manager/n310.py b/mpm/python/usrp_mpm/periph_manager/n310.py index 1bf204218..97157ad1b 100644 --- a/mpm/python/usrp_mpm/periph_manager/n310.py +++ b/mpm/python/usrp_mpm/periph_manager/n310.py @@ -256,4 +256,5 @@ class n310(PeriphManagerBase): self.log.trace( "Updating reference clock on dboard `{}' to {} MHz...".format(slot, ref_clk_freq/1e6) ) + dboard.update_ref_clock_freq(ref_clk_freq) -- cgit v1.2.3