From 54d698e3707cf1be5d38537db783ebadd850e729 Mon Sep 17 00:00:00 2001 From: RobertWalstab Date: Fri, 24 Jul 2020 16:31:45 +0200 Subject: fpga, mpm: Bump FPGA compat number --- mpm/python/usrp_mpm/periph_manager/e31x.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'mpm/python/usrp_mpm/periph_manager/e31x.py') diff --git a/mpm/python/usrp_mpm/periph_manager/e31x.py b/mpm/python/usrp_mpm/periph_manager/e31x.py index 8043fc704..11f65dd17 100644 --- a/mpm/python/usrp_mpm/periph_manager/e31x.py +++ b/mpm/python/usrp_mpm/periph_manager/e31x.py @@ -31,7 +31,7 @@ E310_DEFAULT_CLOCK_SOURCE = 'internal' E310_DEFAULT_TIME_SOURCE = 'internal' E310_DEFAULT_ENABLE_FPGPIO = True E310_DEFAULT_DONT_RELOAD_FPGA = False # False means idle image gets reloaded -E310_FPGA_COMPAT = (5, 0) +E310_FPGA_COMPAT = (6, 0) E310_DBOARD_SLOT_IDX = 0 E310_GPIO_SRC_PS = "PS" # We use the index positions of RFA and RFB to map between name and radio index -- cgit v1.2.3