From fad36514e56c2da459637b5abe261033e40fa8fd Mon Sep 17 00:00:00 2001 From: Mark Meserve Date: Wed, 17 Oct 2018 15:46:41 -0500 Subject: nijesdcore: add variable configuration support --- mpm/python/usrp_mpm/dboard_manager/magnesium.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'mpm/python/usrp_mpm/dboard_manager/magnesium.py') diff --git a/mpm/python/usrp_mpm/dboard_manager/magnesium.py b/mpm/python/usrp_mpm/dboard_manager/magnesium.py index 06dff175f..ca3c74e4b 100644 --- a/mpm/python/usrp_mpm/dboard_manager/magnesium.py +++ b/mpm/python/usrp_mpm/dboard_manager/magnesium.py @@ -422,7 +422,8 @@ class Magnesium(DboardManagerBase): db_clk_control = DboardClockControl(dboard_ctrl_regs, self.log) db_clk_control.reset_mmcm() # Place the JESD204b core in reset, mainly to reset QPLL/CPLLs. - jesdcore = nijesdcore.NIMgJESDCore(dboard_ctrl_regs, self.slot_idx) + jesdcore = nijesdcore.NIJESDCore(dboard_ctrl_regs, self.slot_idx, + **MagnesiumInitManager.JESD_DEFAULT_ARGS) jesdcore.reset() # The reference clock is handled elsewhere since it is a motherboard- # level clock. -- cgit v1.2.3