From d3e6dd11406893bfbc5537dfbe74d8151bbc1280 Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Tue, 12 Dec 2017 09:59:50 -0800 Subject: mpm: Harmonize imports, tidy + sort modules - Moved nijesdcore to cores/ - Moved udev, net, dtoverlay, uio to sys_utils/ - Made all imports non-relative (except in __init__.py files) - Removed some unnecessary imports - Reordered some imports for Python conventions --- mpm/python/usrp_mpm/dboard_manager/eiscat.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'mpm/python/usrp_mpm/dboard_manager/eiscat.py') diff --git a/mpm/python/usrp_mpm/dboard_manager/eiscat.py b/mpm/python/usrp_mpm/dboard_manager/eiscat.py index 15037086f..bfd3b42a9 100644 --- a/mpm/python/usrp_mpm/dboard_manager/eiscat.py +++ b/mpm/python/usrp_mpm/dboard_manager/eiscat.py @@ -21,11 +21,11 @@ EISCAT rx board implementation module import time from builtins import range from builtins import object -from ..mpmlog import get_logger -from ..uio import UIO -from . import lib -from .base import DboardManagerBase -from .lmk_eiscat import LMK04828EISCAT +from usrp_mpm.mpmlog import get_logger +from usrp_mpm.sys_utils.uio import UIO +from usrp_mpm import lib +from usrp_mpm.dboard_manager import DboardManagerBase +from usrp_mpm.dboard_manager.lmk_eiscat import LMK04828EISCAT from usrp_mpm.cores import ClockSynchronizer def create_spidev_iface_sane(dev_node): -- cgit v1.2.3