From f76f599be281d773736940d53aafc6d7e9d536ca Mon Sep 17 00:00:00 2001 From: Ashish Chaudhari Date: Wed, 22 Jul 2015 17:54:17 -0700 Subject: x300: Added a comprehensive radio reset sequence - Everytime the LMK is configured, we do the following: - Reset all LMK regs - Wait for LMK lock - Reset radio_clk PLL in FPGA - Wait for FPGA PLL to lock - Assert radio_rst which resets downstream radio logic - This address the intermittent self-cal failures due to uncalibrated IDELAY taps - Bumped FPGA compat to 12 --- host/lib/usrp/x300/x300_impl.hpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'host/lib/usrp/x300/x300_impl.hpp') diff --git a/host/lib/usrp/x300/x300_impl.hpp b/host/lib/usrp/x300/x300_impl.hpp index ad1c802ee..20cd4d754 100644 --- a/host/lib/usrp/x300/x300_impl.hpp +++ b/host/lib/usrp/x300/x300_impl.hpp @@ -390,10 +390,9 @@ private: void set_time_source_out(mboard_members_t&, const bool); void update_clock_source(mboard_members_t&, const std::string &); void update_time_source(mboard_members_t&, const std::string &); - void reset_radios(mboard_members_t&); uhd::sensor_value_t get_ref_locked(uhd::wb_iface::sptr); - bool wait_for_ref_locked(uhd::wb_iface::sptr, double timeout = 0.0); + bool wait_for_clk_locked(uhd::wb_iface::sptr, boost::uint32_t which, double timeout); bool is_pps_present(uhd::wb_iface::sptr); void set_db_eeprom(uhd::i2c_iface::sptr i2c, const size_t, const uhd::usrp::dboard_eeprom_t &); -- cgit v1.2.3