From ed4223d74cab604213b925da2eccb6055aa7aea2 Mon Sep 17 00:00:00 2001 From: michael-west Date: Thu, 28 Jan 2016 17:31:54 -0800 Subject: UBX: Phase synchronization - Disabled MAX2871 VCO auto selection for phase sync - Added checks for new phase sync constraints recently published by Maxim - Added dboard_clock_rate option for X300 - Adjusted timing of SYNC signal relative to dboard referenc clock --- host/lib/usrp/x300/x300_impl.cpp | 1 + 1 file changed, 1 insertion(+) (limited to 'host/lib/usrp/x300/x300_impl.cpp') diff --git a/host/lib/usrp/x300/x300_impl.cpp b/host/lib/usrp/x300/x300_impl.cpp index ebb9bf3a6..c13c2ac07 100644 --- a/host/lib/usrp/x300/x300_impl.cpp +++ b/host/lib/usrp/x300/x300_impl.cpp @@ -672,6 +672,7 @@ void x300_impl::setup_mb(const size_t mb_i, const uhd::device_addr_t &dev_addr) 1 /*slaveno*/, mb.hw_rev, dev_addr.cast("master_clock_rate", X300_DEFAULT_TICK_RATE), + dev_addr.cast("dboard_clock_rate", X300_DEFAULT_DBOARD_CLK_RATE), dev_addr.cast("system_ref_rate", X300_DEFAULT_SYSREF_RATE)); //Initialize clock source to use internal reference and generate -- cgit v1.2.3