From ed4223d74cab604213b925da2eccb6055aa7aea2 Mon Sep 17 00:00:00 2001 From: michael-west Date: Thu, 28 Jan 2016 17:31:54 -0800 Subject: UBX: Phase synchronization - Disabled MAX2871 VCO auto selection for phase sync - Added checks for new phase sync constraints recently published by Maxim - Added dboard_clock_rate option for X300 - Adjusted timing of SYNC signal relative to dboard referenc clock --- host/lib/usrp/x300/x300_clock_ctrl.hpp | 1 + 1 file changed, 1 insertion(+) (limited to 'host/lib/usrp/x300/x300_clock_ctrl.hpp') diff --git a/host/lib/usrp/x300/x300_clock_ctrl.hpp b/host/lib/usrp/x300/x300_clock_ctrl.hpp index 160a14e6d..7126f1b9f 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.hpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.hpp @@ -48,6 +48,7 @@ public: const size_t slaveno, const size_t hw_rev, const double master_clock_rate, + const double dboard_clock_rate, const double system_ref_rate); /*! Get the master clock rate of the device. -- cgit v1.2.3