From b765df3b1976f30a8b95f5a1ea482517a8000a80 Mon Sep 17 00:00:00 2001 From: michael-west Date: Thu, 25 Sep 2014 15:46:52 -0700 Subject: x300: added reset and resync of ADCs and DACs when changing reference clock --- host/lib/usrp/x300/x300_adc_ctrl.cpp | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) (limited to 'host/lib/usrp/x300/x300_adc_ctrl.cpp') diff --git a/host/lib/usrp/x300/x300_adc_ctrl.cpp b/host/lib/usrp/x300/x300_adc_ctrl.cpp index 75bfb048c..ab2bafef8 100644 --- a/host/lib/usrp/x300/x300_adc_ctrl.cpp +++ b/host/lib/usrp/x300/x300_adc_ctrl.cpp @@ -1,5 +1,5 @@ // -// Copyright 2010-2013 Ettus Research LLC +// Copyright 2010-2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -33,6 +33,11 @@ class x300_adc_ctrl_impl : public x300_adc_ctrl public: x300_adc_ctrl_impl(uhd::spi_iface::sptr iface, const size_t slaveno): _iface(iface), _slaveno(slaveno) + { + init(); + } + + void init() { //power-up adc _ads62p48_regs.reset = 1; @@ -46,8 +51,8 @@ public: _ads62p48_regs.lvds_cmos = ads62p48_regs_t::LVDS_CMOS_DDR_LVDS; _ads62p48_regs.channel_control = ads62p48_regs_t::CHANNEL_CONTROL_INDEPENDENT; _ads62p48_regs.data_format = ads62p48_regs_t::DATA_FORMAT_2S_COMPLIMENT; - _ads62p48_regs.clk_out_pos_edge = ads62p48_regs_t::CLK_OUT_POS_EDGE_MINUS7_26; - _ads62p48_regs.clk_out_neg_edge = ads62p48_regs_t::CLK_OUT_NEG_EDGE_MINUS7_26; + _ads62p48_regs.clk_out_pos_edge = ads62p48_regs_t::CLK_OUT_POS_EDGE_MINUS7_26; + _ads62p48_regs.clk_out_neg_edge = ads62p48_regs_t::CLK_OUT_NEG_EDGE_MINUS7_26; this->send_ads62p48_reg(0); @@ -72,6 +77,11 @@ public: } + void reset() + { + init(); + } + double set_gain(const double &gain) { const meta_range_t gain_range = meta_range_t(0, 6.0, 0.5); -- cgit v1.2.3