From 6855e940f5cfa24de2e1ba294bd8b8f833967e85 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sun, 8 May 2011 20:39:36 +0100 Subject: usrp_e100: work w/ ad9522 clock configuration --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 65162dbeb..460fc5548 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -409,6 +409,7 @@ public: _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF2; _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_MANUAL; this->send_reg(0x01C); + this->latch_regs(); } void use_external_ref(void) { @@ -417,6 +418,7 @@ public: _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF1; _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_MANUAL; this->send_reg(0x01C); + this->latch_regs(); } void use_auto_ref(void) { @@ -424,6 +426,8 @@ public: _ad9522_regs.enable_ref1 = 1; _ad9522_regs.select_ref = ad9522_regs_t::SELECT_REF_REF1; _ad9522_regs.enb_auto_ref_switchover = ad9522_regs_t::ENB_AUTO_REF_SWITCHOVER_AUTO; + this->send_reg(0x01C); + this->latch_regs(); } private: @@ -459,15 +463,27 @@ private: //wait for calibration done: static const boost::uint8_t addr = 0x01F; for (size_t ms10 = 0; ms10 < 100; ms10++){ + boost::this_thread::sleep(boost::posix_time::milliseconds(10)); boost::uint32_t reg = _iface->read_spi( UE_SPI_SS_AD9522, spi_config_t::EDGE_RISE, _ad9522_regs.get_read_reg(addr), 24 ); _ad9522_regs.set_reg(addr, reg); - if (_ad9522_regs.vco_calibration_finished) return; - boost::this_thread::sleep(boost::posix_time::milliseconds(10)); + if (_ad9522_regs.vco_calibration_finished) goto wait_for_ld; } UHD_MSG(error) << "USRP-E100 clock control: VCO calibration timeout" << std::endl; + wait_for_ld: + //wait for digital lock detect: + for (size_t ms10 = 0; ms10 < 100; ms10++){ + boost::this_thread::sleep(boost::posix_time::milliseconds(10)); + boost::uint32_t reg = _iface->read_spi( + UE_SPI_SS_AD9522, spi_config_t::EDGE_RISE, + _ad9522_regs.get_read_reg(addr), 24 + ); + _ad9522_regs.set_reg(addr, reg); + if (_ad9522_regs.digital_lock_detect) return; + } + UHD_MSG(error) << "USRP-E100 clock control: lock detection timeout" << std::endl; } void send_all_regs(void){ -- cgit v1.2.3 From d11bb4e7ba957f14c6449f519576ab7cd85b60bd Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Mon, 9 May 2011 01:12:49 +0100 Subject: usrp-e100: added soft sync for ad9522 clock control --- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 460fc5548..968c2ea04 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -181,6 +181,7 @@ public: _ad9522_regs.ld_pin_control = 0x00; //dld _ad9522_regs.refmon_pin_control = 0x12; //show ref2 _ad9522_regs.lock_detect_counter = ad9522_regs_t::LOCK_DETECT_COUNTER_16CYC; + _ad9522_regs.divider0_ignore_sync = 1; // master FPGA clock ignores sync (always on, cannot be disabled by sync pulse) this->use_internal_ref(); @@ -358,7 +359,7 @@ public: ); this->send_reg(0x199); this->send_reg(0x19a); - this->latch_regs(); + this->soft_sync(); } double get_rx_clock_rate(void){ @@ -393,7 +394,7 @@ public: ); this->send_reg(0x196); this->send_reg(0x197); - this->latch_regs(); + this->soft_sync(); } double get_tx_clock_rate(void){ @@ -486,6 +487,15 @@ private: UHD_MSG(error) << "USRP-E100 clock control: lock detection timeout" << std::endl; } + void soft_sync(void){ + _ad9522_regs.soft_sync = 1; + this->send_reg(0x230); + this->latch_regs(); + _ad9522_regs.soft_sync = 0; + this->send_reg(0x230); + this->latch_regs(); + } + void send_all_regs(void){ //setup a list of register ranges to write typedef std::pair range_t; -- cgit v1.2.3 From b60418e93a8c473372d14cd5fdf430afa6e8fed4 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 12 May 2011 15:34:24 -0700 Subject: usrp-e100: created device address arg for master clock rate, removed eeprom hack --- host/docs/usrp_e1xx.rst | 15 ++++++--------- host/lib/usrp/mboard_eeprom.cpp | 29 +---------------------------- host/lib/usrp/usrp_e100/clock_ctrl.cpp | 28 ++++++---------------------- host/lib/usrp/usrp_e100/clock_ctrl.hpp | 3 ++- host/lib/usrp/usrp_e100/mboard_impl.cpp | 3 ++- host/lib/usrp/usrp_e100/usrp_e100_impl.cpp | 3 ++- 6 files changed, 19 insertions(+), 62 deletions(-) (limited to 'host/lib/usrp/usrp_e100/clock_ctrl.cpp') diff --git a/host/docs/usrp_e1xx.rst b/host/docs/usrp_e1xx.rst index 036d2c02c..fcaa57716 100644 --- a/host/docs/usrp_e1xx.rst +++ b/host/docs/usrp_e1xx.rst @@ -35,12 +35,7 @@ To use the 61.44MHz clock rate, the USRP embedded will require two jumpers to be * J16 is a two pin header, remove the jumper (or leave it on pin1 only) * J15 is a three pin header, move the jumper to (pin1, pin2) -Then run the following commands to record the setting into the EEPROM: -:: - - cd /share/uhd/utils - ./usrp_burn_mb_eeprom --key=mcr --val=61.44e6 - +**Note:** See instructions below to communicate the desired clock rate into the UHD. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Set other rates - uses internal VCO @@ -50,11 +45,13 @@ To use other clock rates, the jumpers will need to be in the default position. * J16 is a two pin header, move the jumper to (pin1, pin2) * J15 is a three pin header, move the jumper to (pin2, pin3) -Then run the following commands to record the setting into the EEPROM: +To communicate the desired clock rate into the UHD, +specify the a special device address argument, +where the key is "master_clock_rate" and the value is a rate in Hz. +Example: :: - cd /share/uhd/utils - ./usrp_burn_mb_eeprom --key=mcr --val= + uhd_usrp_probe --args="master_clock_rate=52e6" ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Clock rate recovery - unbricking diff --git a/host/lib/usrp/mboard_eeprom.cpp b/host/lib/usrp/mboard_eeprom.cpp index 297de990f..2ee4a9284 100644 --- a/host/lib/usrp/mboard_eeprom.cpp +++ b/host/lib/usrp/mboard_eeprom.cpp @@ -252,8 +252,7 @@ struct e100_eeprom_map{ unsigned char env_var[16]; unsigned char env_setting[64]; unsigned char serial[10]; - unsigned char name[16]; - unsigned char mcr[sizeof(float)]; + unsigned char name[NAME_MAX_LEN]; }; template static const byte_vector_t to_bytes(const T &item){ @@ -285,20 +284,6 @@ static void load_e100(mboard_eeprom_t &mb_eeprom, i2c_iface &iface){ load_e100_string_xx(env_setting); load_e100_string_xx(serial); load_e100_string_xx(name); - - //extract the master clock rate - float master_clock_rate = 0; - const byte_vector_t rate_bytes = iface.read_eeprom( - E100_EEPROM_ADDR, offsetof(e100_eeprom_map, mcr), sizeof(master_clock_rate) - ); - std::copy( - rate_bytes.begin(), rate_bytes.end(), //source - reinterpret_cast(&master_clock_rate) //destination - ); - if (master_clock_rate > 1e6 and master_clock_rate < 1e9){ - mb_eeprom["mcr"] = boost::lexical_cast(master_clock_rate); - } - else mb_eeprom["mcr"] = ""; } static void store_e100(const mboard_eeprom_t &mb_eeprom, i2c_iface &iface){ @@ -333,18 +318,6 @@ static void store_e100(const mboard_eeprom_t &mb_eeprom, i2c_iface &iface){ store_e100_string_xx(env_setting); store_e100_string_xx(serial); store_e100_string_xx(name); - - //store the master clock rate - if (mb_eeprom.has_key("mcr")){ - const float master_clock_rate = float(boost::lexical_cast(mb_eeprom["mcr"])); - const byte_vector_t rate_bytes( - reinterpret_cast(&master_clock_rate), - reinterpret_cast(&master_clock_rate) + sizeof(master_clock_rate) - ); - iface.write_eeprom( - E100_EEPROM_ADDR, offsetof(e100_eeprom_map, mcr), rate_bytes - ); - } } /*********************************************************************** diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/usrp_e100/clock_ctrl.cpp index 968c2ea04..49ce0c742 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.cpp @@ -37,7 +37,6 @@ using namespace uhd; **********************************************************************/ static const bool ENABLE_THE_TEST_OUT = true; static const double REFERENCE_INPUT_RATE = 10e6; -static const double DEFAULT_OUTPUT_RATE = 64e6; /*********************************************************************** * Helpers @@ -168,7 +167,7 @@ static clock_settings_type get_clock_settings(double rate){ **********************************************************************/ class usrp_e100_clock_ctrl_impl : public usrp_e100_clock_ctrl{ public: - usrp_e100_clock_ctrl_impl(usrp_e100_iface::sptr iface){ + usrp_e100_clock_ctrl_impl(usrp_e100_iface::sptr iface, double master_clock_rate){ _iface = iface; _chan_rate = 0.0; _out_rate = 0.0; @@ -185,24 +184,9 @@ public: this->use_internal_ref(); - //initialize the FPGA clock to something - bool fpga_clock_initialized = false; - try{ - if (not _iface->mb_eeprom["mcr"].empty()){ - UHD_MSG(status) << "Read FPGA clock rate from EEPROM setting." << std::endl; - const double master_clock_rate = boost::lexical_cast(_iface->mb_eeprom["mcr"]); - UHD_MSG(status) << boost::format("Initializing FPGA clock to %fMHz...") % (master_clock_rate/1e6) << std::endl; - this->set_fpga_clock_rate(master_clock_rate); - fpga_clock_initialized = true; - } - } - catch(const std::exception &e){ - UHD_MSG(error) << "Error setting FPGA clock rate from EEPROM: " << e.what() << std::endl; - } - if (not fpga_clock_initialized){ //was not set... use the default rate - UHD_MSG(status) << boost::format("Initializing FPGA clock to %fMHz...") % (DEFAULT_OUTPUT_RATE/1e6) << std::endl; - this->set_fpga_clock_rate(DEFAULT_OUTPUT_RATE); - } + //initialize the FPGA clock rate + UHD_MSG(status) << boost::format("Initializing FPGA clock to %fMHz...") % (master_clock_rate/1e6) << std::endl; + this->set_fpga_clock_rate(master_clock_rate); this->enable_test_clock(ENABLE_THE_TEST_OUT); this->enable_rx_dboard_clock(false); @@ -518,6 +502,6 @@ private: /*********************************************************************** * Clock Control Make **********************************************************************/ -usrp_e100_clock_ctrl::sptr usrp_e100_clock_ctrl::make(usrp_e100_iface::sptr iface){ - return sptr(new usrp_e100_clock_ctrl_impl(iface)); +usrp_e100_clock_ctrl::sptr usrp_e100_clock_ctrl::make(usrp_e100_iface::sptr iface, double master_clock_rate){ + return sptr(new usrp_e100_clock_ctrl_impl(iface, master_clock_rate)); } diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.hpp b/host/lib/usrp/usrp_e100/clock_ctrl.hpp index 507f914f3..6f16bc6ed 100644 --- a/host/lib/usrp/usrp_e100/clock_ctrl.hpp +++ b/host/lib/usrp/usrp_e100/clock_ctrl.hpp @@ -35,9 +35,10 @@ public: /*! * Make a new clock control object. * \param iface the usrp_e100 iface object + * \param master clock rate the FPGA rate * \return the clock control object */ - static sptr make(usrp_e100_iface::sptr iface); + static sptr make(usrp_e100_iface::sptr iface, double master_clock_rate); /*! * Set the rate of the fpga clock line. diff --git a/host/lib/usrp/usrp_e100/mboard_impl.cpp b/host/lib/usrp/usrp_e100/mboard_impl.cpp index d31662eb5..b2533e7ee 100644 --- a/host/lib/usrp/usrp_e100/mboard_impl.cpp +++ b/host/lib/usrp/usrp_e100/mboard_impl.cpp @@ -209,7 +209,8 @@ void usrp_e100_impl::mboard_set(const wax::obj &key, const wax::obj &val){ case MBOARD_PROP_CLOCK_RATE: UHD_MSG(warning) << "I see that you are setting the master clock rate from the API.\n" - << "You may find it more convenient to burn this setting into the EEPROM.\n" + << "You may want to pass this into the device address as mcr=.\n" + << "This way, the clock rate is guaranteed to be initialized first.\n" << "See the application notes for USRP-E1XX for further instructions.\n" ; _clock_ctrl->set_fpga_clock_rate(val.as()); diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp index 4247746ab..5fba0c153 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp @@ -156,7 +156,8 @@ usrp_e100_impl::usrp_e100_impl( { //setup interfaces into hardware - _clock_ctrl = usrp_e100_clock_ctrl::make(_iface); + const double master_clock_rate = device_addr.cast("master_clock_rate", 64e6); + _clock_ctrl = usrp_e100_clock_ctrl::make(_iface, master_clock_rate); _codec_ctrl = usrp_e100_codec_ctrl::make(_iface); //initialize the mboard -- cgit v1.2.3