From ac85d2b38c26fd6d31ba0a997d033b159d51769d Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Fri, 13 Aug 2010 01:09:45 +0000 Subject: usrp-e: codec gain control from properties interface --- host/lib/usrp/usrp_e/clock_ctrl.cpp | 1 - 1 file changed, 1 deletion(-) (limited to 'host/lib/usrp/usrp_e/clock_ctrl.cpp') diff --git a/host/lib/usrp/usrp_e/clock_ctrl.cpp b/host/lib/usrp/usrp_e/clock_ctrl.cpp index 8a5bd1c6b..b53e880a2 100644 --- a/host/lib/usrp/usrp_e/clock_ctrl.cpp +++ b/host/lib/usrp/usrp_e/clock_ctrl.cpp @@ -60,7 +60,6 @@ class usrp_e_clock_ctrl_impl : public usrp_e_clock_ctrl{ public: usrp_e_clock_ctrl_impl(usrp_e_iface::sptr iface){ _iface = iface; - std::cout << "master_clock_rate: " << (master_clock_rate/1e6) << " MHz" << std::endl; //init the clock gen registers //Note: out0 should already be clocking the FPGA or this isnt going to work -- cgit v1.2.3