From 38248b816c75bcf60eca69244d363cae2397ce47 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 31 Mar 2010 17:43:20 -0700 Subject: Refactor ATR part of dboard interface (and some constants). Added peek and poke to the dude/bro protocol. Started moving more control code through peek and poke. Added usrp_regs.hpp to be like memory map for slave perifs. --- host/lib/usrp/usrp2/usrp2_regs.hpp | 57 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 host/lib/usrp/usrp2/usrp2_regs.hpp (limited to 'host/lib/usrp/usrp2/usrp2_regs.hpp') diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp new file mode 100644 index 000000000..9cf0b1fbc --- /dev/null +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -0,0 +1,57 @@ +// +// Copyright 2010 Ettus Research LLC +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef INCLUDED_USRP2_REGS_HPP +#define INCLUDED_USRP2_REGS_HPP + +#include + +//////////////////////////////////////////////// +// GPIO, Slave 4 +// +// These go to the daughterboard i/o pins + +#define GPIO_BASE 0xC800 + +typedef struct { + boost::uint32_t io; // tx data in high 16, rx in low 16 + boost::uint32_t ddr; // 32 bits, 1 means output. tx in high 16, rx in low 16 + boost::uint32_t tx_sel; // 16 2-bit fields select which source goes to TX DB + boost::uint32_t rx_sel; // 16 2-bit fields select which source goes to RX DB +} gpio_regs_t; + +// each 2-bit sel field is layed out this way +#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg +#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic +#define GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric +#define GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric + +/////////////////////////////////////////////////// +// ATR Controller, Slave 11 + +#define ATR_BASE 0xE400 + +typedef struct { + boost::uint32_t v[16]; +} atr_regs_t; + +#define ATR_IDLE 0x0 // indicies into v +#define ATR_TX 0x1 +#define ATR_RX 0x2 +#define ATR_FULL 0x3 + +#endif /* INCLUDED_USRP2_REGS_HPP */ -- cgit v1.2.3 From f15df8146cffb6cf42e0365396484af085be5df4 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 31 Mar 2010 18:55:48 -0700 Subject: Moved dsp (rx and tx), time config, and clock config (mostly) into the host. --- firmware/microblaze/apps/txrx.c | 116 ------------------------ host/lib/usrp/usrp2/dboard_impl.cpp | 30 +++---- host/lib/usrp/usrp2/dsp_impl.cpp | 56 ++++++------ host/lib/usrp/usrp2/fw_common.h | 56 ------------ host/lib/usrp/usrp2/mboard_impl.cpp | 56 +++++------- host/lib/usrp/usrp2/usrp2_impl.hpp | 3 +- host/lib/usrp/usrp2/usrp2_regs.hpp | 173 ++++++++++++++++++++++++++++++++++-- 7 files changed, 231 insertions(+), 259 deletions(-) (limited to 'host/lib/usrp/usrp2/usrp2_regs.hpp') diff --git a/firmware/microblaze/apps/txrx.c b/firmware/microblaze/apps/txrx.c index 926260bac..430ae2fac 100644 --- a/firmware/microblaze/apps/txrx.c +++ b/firmware/microblaze/apps/txrx.c @@ -249,47 +249,6 @@ void handle_udp_ctrl_packet( ctrl_data_out.data.dboard_ids.rx_id = read_dboard_eeprom(I2C_ADDR_RX_A); break; - /******************************************************************* - * Clock Config - ******************************************************************/ - case USRP2_CTRL_ID_HERES_A_NEW_CLOCK_CONFIG_BRO: - //TODO handle MC_PROVIDE_CLK_TO_MIMO when we do MIMO setup - ctrl_data_out.id = USRP2_CTRL_ID_GOT_THE_NEW_CLOCK_CONFIG_DUDE; - - //handle the 10 mhz ref source - uint32_t ref_flags = 0; - switch(ctrl_data_out.data.clock_config.ref_source){ - case USRP2_REF_SOURCE_INT: - ref_flags = MC_WE_DONT_LOCK; break; - case USRP2_REF_SOURCE_SMA: - ref_flags = MC_WE_LOCK_TO_SMA; break; - case USRP2_REF_SOURCE_MIMO: - ref_flags = MC_WE_LOCK_TO_MIMO; break; - } - clocks_mimo_config(ref_flags & MC_REF_CLK_MASK); - - //handle the pps config - uint32_t pps_flags = 0; - - //fill in the pps polarity flags - switch(ctrl_data_out.data.clock_config.pps_polarity){ - case USRP2_PPS_POLARITY_POS: - pps_flags |= 0x01 << 0; break; - case USRP2_PPS_POLARITY_NEG: - pps_flags |= 0x00 << 0; break; - } - - //fill in the pps source flags - switch(ctrl_data_out.data.clock_config.pps_source){ - case USRP2_PPS_SOURCE_SMA: - pps_flags |= 0x00 << 1; break; - case USRP2_PPS_SOURCE_MIMO: - pps_flags |= 0x01 << 1; break; - } - sr_time64->flags = pps_flags; - - break; - /******************************************************************* * SPI ******************************************************************/ @@ -385,34 +344,6 @@ void handle_udp_ctrl_packet( ctrl_data_out.id = USRP2_CTRL_ID_DONE_WITH_THAT_AUX_ADC_DUDE; break; - /******************************************************************* - * DDC - ******************************************************************/ - case USRP2_CTRL_ID_SETUP_THIS_DDC_FOR_ME_BRO: - dsp_rx_regs->freq = ctrl_data_in->data.ddc_args.freq_word; - dsp_rx_regs->scale_iq = ctrl_data_in->data.ddc_args.scale_iq; - - //setup the interp and half band filters - { - uint32_t decim = ctrl_data_in->data.ddc_args.decim; - uint32_t hb1 = 0; - uint32_t hb2 = 0; - if (!(decim & 1)){ - hb2 = 1; - decim = decim >> 1; - } - if (!(decim & 1)){ - hb1 = 1; - decim = decim >> 1; - } - uint32_t decim_word = (hb1<<9) | (hb2<<8) | decim; - dsp_rx_regs->decim_rate = decim_word; - printf("Decim: %d, register %d\n", ctrl_data_in->data.ddc_args.decim, decim_word); - } - - ctrl_data_out.id = USRP2_CTRL_ID_TOTALLY_SETUP_THE_DDC_DUDE; - break; - /******************************************************************* * Streaming ******************************************************************/ @@ -477,53 +408,6 @@ void handle_udp_ctrl_packet( break; } - /******************************************************************* - * DUC - ******************************************************************/ - case USRP2_CTRL_ID_SETUP_THIS_DUC_FOR_ME_BRO: - dsp_tx_regs->freq = ctrl_data_in->data.duc_args.freq_word; - dsp_tx_regs->scale_iq = ctrl_data_in->data.duc_args.scale_iq; - - //setup the interp and half band filters - { - uint32_t interp = ctrl_data_in->data.duc_args.interp; - uint32_t hb1 = 0; - uint32_t hb2 = 0; - if (!(interp & 1)){ - hb2 = 1; - interp = interp >> 1; - } - if (!(interp & 1)){ - hb1 = 1; - interp = interp >> 1; - } - uint32_t interp_word = (hb1<<9) | (hb2<<8) | interp; - dsp_tx_regs->interp_rate = interp_word; - printf("Interp: %d, register %d\n", ctrl_data_in->data.duc_args.interp, interp_word); - } - - ctrl_data_out.id = USRP2_CTRL_ID_TOTALLY_SETUP_THE_DUC_DUDE; - break; - - /******************************************************************* - * Time Config - ******************************************************************/ - case USRP2_CTRL_ID_GOT_A_NEW_TIME_FOR_YOU_BRO: - sr_time64->imm = (ctrl_data_in->data.time_args.now == 0)? 0 : 1; - sr_time64->ticks = ctrl_data_in->data.time_args.ticks; - sr_time64->secs = ctrl_data_in->data.time_args.secs; //set this last to latch the regs - ctrl_data_out.id = USRP2_CTRL_ID_SWEET_I_GOT_THAT_TIME_DUDE; - break; - - /******************************************************************* - * MUX Config - ******************************************************************/ - case USRP2_CTRL_ID_UPDATE_THOSE_MUX_SETTINGS_BRO: - dsp_rx_regs->rx_mux = ctrl_data_in->data.mux_args.rx_mux; - dsp_tx_regs->tx_mux = ctrl_data_in->data.mux_args.tx_mux; - ctrl_data_out.id = USRP2_CTRL_ID_UPDATED_THE_MUX_SETTINGS_DUDE; - break; - /******************************************************************* * Peek and Poke Register ******************************************************************/ diff --git a/host/lib/usrp/usrp2/dboard_impl.cpp b/host/lib/usrp/usrp2/dboard_impl.cpp index fd72aeaa4..86ee52594 100644 --- a/host/lib/usrp/usrp2/dboard_impl.cpp +++ b/host/lib/usrp/usrp2/dboard_impl.cpp @@ -15,10 +15,12 @@ // along with this program. If not, see . // + +#include "usrp2_impl.hpp" +#include "usrp2_regs.hpp" #include -#include #include -#include "usrp2_impl.hpp" +#include using namespace uhd; using namespace uhd::usrp; @@ -57,11 +59,13 @@ void usrp2_impl::dboard_init(void){ //init the subdevs in use (use the first subdevice) _rx_subdevs_in_use = prop_names_t(1, _dboard_manager->get_rx_subdev_names().at(0)); + update_rx_mux_config(); + _tx_subdevs_in_use = prop_names_t(1, _dboard_manager->get_tx_subdev_names().at(0)); - update_mux_config(); + update_tx_mux_config(); } -void usrp2_impl::update_mux_config(void){ +void usrp2_impl::update_rx_mux_config(void){ //calculate the rx mux boost::uint32_t rx_mux = 0; ASSERT_THROW(_rx_subdevs_in_use.size() == 1); @@ -76,6 +80,10 @@ void usrp2_impl::update_mux_config(void){ rx_mux = (((rx_mux >> 0) & 0x3) << 2) | (((rx_mux >> 2) & 0x3) << 0); } + this->poke(offsetof(dsp_rx_regs_t, rx_mux) + DSP_RX_BASE, rx_mux); +} + +void usrp2_impl::update_tx_mux_config(void){ //calculate the tx mux boost::uint32_t tx_mux = 0x10; ASSERT_THROW(_tx_subdevs_in_use.size() == 1); @@ -85,15 +93,7 @@ void usrp2_impl::update_mux_config(void){ tx_mux = (((tx_mux >> 0) & 0x1) << 1) | (((tx_mux >> 1) & 0x1) << 0); } - //setup the out data - usrp2_ctrl_data_t out_data; - out_data.id = htonl(USRP2_CTRL_ID_UPDATE_THOSE_MUX_SETTINGS_BRO); - out_data.data.mux_args.rx_mux = htonl(rx_mux); - out_data.data.mux_args.tx_mux = htonl(tx_mux); - - //send and recv - usrp2_ctrl_data_t in_data = ctrl_send_and_recv(out_data); - ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_UPDATED_THE_MUX_SETTINGS_DUDE); + this->poke(offsetof(dsp_tx_regs_t, tx_mux) + DSP_TX_BASE, tx_mux); } /*********************************************************************** @@ -129,7 +129,7 @@ void usrp2_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){ void usrp2_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){ if (key.as() == DBOARD_PROP_USED_SUBDEVS){ _rx_subdevs_in_use = val.as(); - update_mux_config(); //if the val is bad, this will throw + update_rx_mux_config(); //if the val is bad, this will throw return; } @@ -169,7 +169,7 @@ void usrp2_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){ void usrp2_impl::tx_dboard_set(const wax::obj &key, const wax::obj &val){ if (key.as() == DBOARD_PROP_USED_SUBDEVS){ _tx_subdevs_in_use = val.as(); - update_mux_config(); //if the val is bad, this will throw + update_tx_mux_config(); //if the val is bad, this will throw return; } diff --git a/host/lib/usrp/usrp2/dsp_impl.cpp b/host/lib/usrp/usrp2/dsp_impl.cpp index 0d43fac0e..6edfec61a 100644 --- a/host/lib/usrp/usrp2/dsp_impl.cpp +++ b/host/lib/usrp/usrp2/dsp_impl.cpp @@ -15,11 +15,13 @@ // along with this program. If not, see . // +#include "usrp2_impl.hpp" +#include "usrp2_regs.hpp" #include #include #include #include -#include "usrp2_impl.hpp" +#include using namespace uhd; @@ -64,25 +66,25 @@ void usrp2_impl::init_ddc_config(void){ update_ddc_config(); //initial command that kills streaming (in case if was left on) - //issue_ddc_stream_cmd(TODO) + stream_cmd_t stream_cmd_off; + stream_cmd_off.stream_now = true; + stream_cmd_off.continuous = false; + stream_cmd_off.num_samps = 0; + issue_ddc_stream_cmd(stream_cmd_off); } void usrp2_impl::update_ddc_config(void){ - //setup the out data - usrp2_ctrl_data_t out_data; - out_data.id = htonl(USRP2_CTRL_ID_SETUP_THIS_DDC_FOR_ME_BRO); - out_data.data.ddc_args.freq_word = htonl( - calculate_freq_word_and_update_actual_freq(_ddc_freq, get_master_clock_freq()) + //set the decimation + this->poke( + offsetof(dsp_rx_regs_t, decim_rate) + DSP_RX_BASE, _ddc_decim ); - out_data.data.ddc_args.decim = htonl(_ddc_decim); + + //set the scaling static const boost::int16_t default_rx_scale_iq = 1024; - out_data.data.ddc_args.scale_iq = htonl( + this->poke( + offsetof(dsp_rx_regs_t, scale_iq) + DSP_RX_BASE, calculate_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq) ); - - //send and recv - usrp2_ctrl_data_t in_data = ctrl_send_and_recv(out_data); - ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_TOTALLY_SETUP_THE_DDC_DUDE); } void usrp2_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd){ @@ -172,7 +174,10 @@ void usrp2_impl::ddc_set(const wax::obj &key, const wax::obj &val){ ASSERT_THROW(new_freq <= get_master_clock_freq()/2.0); ASSERT_THROW(new_freq >= -get_master_clock_freq()/2.0); _ddc_freq = new_freq; //shadow - update_ddc_config(); + this->poke( //set the cordic + offsetof(dsp_rx_regs_t, freq) + DSP_RX_BASE, + calculate_freq_word_and_update_actual_freq(_ddc_freq, get_master_clock_freq()) + ); return; } else if (key_name == "stream_cmd"){ @@ -210,20 +215,16 @@ void usrp2_impl::update_duc_config(void){ double interp_cubed = std::pow(double(tmp_interp), 3); boost::int16_t scale = rint((4096*std::pow(2, ceil(log2(interp_cubed))))/(1.65*interp_cubed)); - //setup the out data - usrp2_ctrl_data_t out_data; - out_data.id = htonl(USRP2_CTRL_ID_SETUP_THIS_DUC_FOR_ME_BRO); - out_data.data.duc_args.freq_word = htonl( - calculate_freq_word_and_update_actual_freq(_duc_freq, get_master_clock_freq()) + //set the interpolation + this->poke( + offsetof(dsp_tx_regs_t, interp_rate) + DSP_TX_BASE, _ddc_decim ); - out_data.data.duc_args.interp = htonl(_duc_interp); - out_data.data.duc_args.scale_iq = htonl( + + //set the scaling + this->poke( + offsetof(dsp_tx_regs_t, scale_iq) + DSP_TX_BASE, calculate_iq_scale_word(scale, scale) ); - - //send and recv - usrp2_ctrl_data_t in_data = ctrl_send_and_recv(out_data); - ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_TOTALLY_SETUP_THE_DUC_DUDE); } /*********************************************************************** @@ -297,7 +298,10 @@ void usrp2_impl::duc_set(const wax::obj &key, const wax::obj &val){ ASSERT_THROW(new_freq <= get_master_clock_freq()/2.0); ASSERT_THROW(new_freq >= -get_master_clock_freq()/2.0); _duc_freq = new_freq; //shadow - update_duc_config(); + this->poke( //set the cordic + offsetof(dsp_tx_regs_t, freq) + DSP_TX_BASE, + calculate_freq_word_and_update_actual_freq(_duc_freq, get_master_clock_freq()) + ); return; } diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h index 565154305..c168614ee 100644 --- a/host/lib/usrp/usrp2/fw_common.h +++ b/host/lib/usrp/usrp2/fw_common.h @@ -60,9 +60,6 @@ typedef enum{ USRP2_CTRL_ID_GIVE_ME_YOUR_DBOARD_IDS_BRO = 'd', USRP2_CTRL_ID_THESE_ARE_MY_DBOARD_IDS_DUDE = 'D', - USRP2_CTRL_ID_HERES_A_NEW_CLOCK_CONFIG_BRO = 'c', - USRP2_CTRL_ID_GOT_THE_NEW_CLOCK_CONFIG_DUDE = 'C', - USRP2_CTRL_ID_TRANSACT_ME_SOME_SPI_BRO = 's', USRP2_CTRL_ID_OMG_TRANSACTED_SPI_DUDE = 'S', @@ -78,21 +75,9 @@ typedef enum{ USRP2_CTRL_ID_READ_FROM_THIS_AUX_ADC_BRO = 'y', USRP2_CTRL_ID_DONE_WITH_THAT_AUX_ADC_DUDE = 'Y', - USRP2_CTRL_ID_SETUP_THIS_DDC_FOR_ME_BRO = '\\', - USRP2_CTRL_ID_TOTALLY_SETUP_THE_DDC_DUDE = '/', - USRP2_CTRL_ID_SEND_STREAM_COMMAND_FOR_ME_BRO = '{', USRP2_CTRL_ID_GOT_THAT_STREAM_COMMAND_DUDE = '}', - USRP2_CTRL_ID_SETUP_THIS_DUC_FOR_ME_BRO = '\'', - USRP2_CTRL_ID_TOTALLY_SETUP_THE_DUC_DUDE = '"', - - USRP2_CTRL_ID_GOT_A_NEW_TIME_FOR_YOU_BRO = '<', - USRP2_CTRL_ID_SWEET_I_GOT_THAT_TIME_DUDE = '>', - - USRP2_CTRL_ID_UPDATE_THOSE_MUX_SETTINGS_BRO = '-', - USRP2_CTRL_ID_UPDATED_THE_MUX_SETTINGS_DUDE = '_', - USRP2_CTRL_ID_POKE_THIS_REGISTER_FOR_ME_BRO = 'p', USRP2_CTRL_ID_OMG_POKED_REGISTER_SO_BAD_DUDE = 'P', @@ -103,22 +88,6 @@ typedef enum{ } usrp2_ctrl_id_t; -typedef enum{ - USRP2_PPS_SOURCE_SMA, - USRP2_PPS_SOURCE_MIMO -} usrp2_pps_source_t; - -typedef enum{ - USRP2_PPS_POLARITY_POS, - USRP2_PPS_POLARITY_NEG -} usrp2_pps_polarity_t; - -typedef enum{ - USRP2_REF_SOURCE_INT, - USRP2_REF_SOURCE_SMA, - USRP2_REF_SOURCE_MIMO -} usrp2_ref_source_t; - typedef enum{ USRP2_DIR_RX, USRP2_DIR_TX @@ -139,12 +108,6 @@ typedef struct{ _SINS_ uint16_t rx_id; _SINS_ uint16_t tx_id; } dboard_ids; - struct { - _SINS_ uint8_t pps_source; - _SINS_ uint8_t pps_polarity; - _SINS_ uint8_t ref_source; - _SINS_ uint8_t _pad; - } clock_config; struct { _SINS_ uint8_t dev; _SINS_ uint8_t edge; @@ -163,11 +126,6 @@ typedef struct{ _SINS_ uint8_t _pad[2]; _SINS_ uint32_t value; } aux_args; - struct { - _SINS_ uint32_t freq_word; - _SINS_ uint32_t decim; - _SINS_ uint32_t scale_iq; - } ddc_args; struct { _SINS_ uint8_t now; //stream now? _SINS_ uint8_t continuous; //auto-reload commmands? @@ -176,20 +134,6 @@ typedef struct{ _SINS_ uint32_t ticks; _SINS_ uint32_t num_samps; } stream_cmd; - struct { - _SINS_ uint32_t freq_word; - _SINS_ uint32_t interp; - _SINS_ uint32_t scale_iq; - } duc_args; - struct { - _SINS_ uint32_t secs; - _SINS_ uint32_t ticks; - _SINS_ uint8_t now; - } time_args; - struct { - _SINS_ uint32_t rx_mux; - _SINS_ uint32_t tx_mux; - } mux_args; struct { _SINS_ uint32_t addr; _SINS_ uint32_t data; diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index 35dfd6287..eff53c5b2 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -15,9 +15,12 @@ // along with this program. If not, see . // +#include "usrp2_impl.hpp" +#include "usrp2_regs.hpp" #include #include -#include "usrp2_impl.hpp" +#include +#include using namespace uhd; @@ -46,55 +49,36 @@ void usrp2_impl::init_clock_config(void){ } void usrp2_impl::update_clock_config(void){ - //setup the out data - usrp2_ctrl_data_t out_data; - out_data.id = htonl(USRP2_CTRL_ID_HERES_A_NEW_CLOCK_CONFIG_BRO); - - //translate ref source enums - switch(_clock_config.ref_source){ - case clock_config_t::REF_INT: - out_data.data.clock_config.ref_source = USRP2_REF_SOURCE_INT; break; - case clock_config_t::REF_SMA: - out_data.data.clock_config.ref_source = USRP2_REF_SOURCE_SMA; break; - case clock_config_t::REF_MIMO: - out_data.data.clock_config.ref_source = USRP2_REF_SOURCE_MIMO; break; - default: throw std::runtime_error("usrp2: unhandled clock configuration ref source"); - } + boost::uint32_t pps_flags = 0; //translate pps source enums switch(_clock_config.pps_source){ - case clock_config_t::PPS_SMA: - out_data.data.clock_config.pps_source = USRP2_PPS_SOURCE_SMA; break; - case clock_config_t::PPS_MIMO: - out_data.data.clock_config.pps_source = USRP2_PPS_SOURCE_MIMO; break; + case clock_config_t::PPS_SMA: pps_flags |= PPS_FLAG_SMA; break; + case clock_config_t::PPS_MIMO: pps_flags |= PPS_FLAG_MIMO; break; default: throw std::runtime_error("usrp2: unhandled clock configuration pps source"); } //translate pps polarity enums switch(_clock_config.pps_polarity){ - case clock_config_t::PPS_POS: - out_data.data.clock_config.pps_source = USRP2_PPS_POLARITY_POS; break; - case clock_config_t::PPS_NEG: - out_data.data.clock_config.pps_source = USRP2_PPS_POLARITY_NEG; break; + case clock_config_t::PPS_POS: pps_flags |= PPS_FLAG_POSEDGE; break; + case clock_config_t::PPS_NEG: pps_flags |= PPS_FLAG_NEGEDGE; break; default: throw std::runtime_error("usrp2: unhandled clock configuration pps polarity"); } - //send and recv - usrp2_ctrl_data_t in_data = ctrl_send_and_recv(out_data); - ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_GOT_THE_NEW_CLOCK_CONFIG_DUDE); + //set the pps flags + this->poke(offsetof(sr_time64_t, flags) + TIME64_BASE, pps_flags); + + //TODO clock source ref 10mhz (spi ad9510) } void usrp2_impl::set_time_spec(const time_spec_t &time_spec, bool now){ - //setup the out data - usrp2_ctrl_data_t out_data; - out_data.id = htonl(USRP2_CTRL_ID_GOT_A_NEW_TIME_FOR_YOU_BRO); - out_data.data.time_args.secs = htonl(time_spec.secs); - out_data.data.time_args.ticks = htonl(time_spec.ticks); - out_data.data.time_args.now = (now)? 1 : 0; - - //send and recv - usrp2_ctrl_data_t in_data = ctrl_send_and_recv(out_data); - ASSERT_THROW(htonl(in_data.id) == USRP2_CTRL_ID_SWEET_I_GOT_THAT_TIME_DUDE); + //set ticks and seconds + this->poke(offsetof(sr_time64_t, secs) + TIME64_BASE, time_spec.secs); + this->poke(offsetof(sr_time64_t, ticks) + TIME64_BASE, time_spec.ticks); + + //set the register to latch it all in + boost::uint32_t imm_flags = (now)? TIME64_LATCH_NOW : TIME64_LATCH_NEXT_PPS; + this->poke(offsetof(sr_time64_t, imm) + TIME64_BASE, imm_flags); } /*********************************************************************** diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp index 1b6175195..55be420cd 100644 --- a/host/lib/usrp/usrp2/usrp2_impl.hpp +++ b/host/lib/usrp/usrp2/usrp2_impl.hpp @@ -172,7 +172,8 @@ private: void tx_dboard_set(const wax::obj &, const wax::obj &); uhd::dict _tx_dboards; uhd::prop_names_t _tx_subdevs_in_use; - void update_mux_config(void); + void update_rx_mux_config(void); + void update_tx_mux_config(void); //methods and shadows for the ddc dsp std::vector _allowed_decim_and_interp_rates; diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index 9cf0b1fbc..7d868c264 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -20,6 +20,161 @@ #include +//////////////////////////////////////////////////// +// Settings Bus, Slave #7, Not Byte Addressable! +// +// Output-only from processor point-of-view. +// 1KB of address space (== 256 32-bit write-only regs) + + +#define MISC_OUTPUT_BASE 0xD400 +#define TX_PROTOCOL_ENGINE_BASE 0xD480 +#define RX_PROTOCOL_ENGINE_BASE 0xD4C0 +#define BUFFER_POOL_CTRL_BASE 0xD500 +#define LAST_SETTING_REG 0xD7FC // last valid setting register + +#define SR_MISC 0 +#define SR_TX_PROT_ENG 32 +#define SR_RX_PROT_ENG 48 +#define SR_BUFFER_POOL_CTRL 64 +#define SR_UDP_SM 96 +#define SR_TX_DSP 208 +#define SR_TX_CTRL 224 +#define SR_RX_DSP 160 +#define SR_RX_CTRL 176 +#define SR_TIME64 192 +#define SR_SIMTIMER 198 +#define SR_LAST 255 + +#define _SR_ADDR(sr) (MISC_OUTPUT_BASE + (sr) * sizeof(uint32_t)) + +///////////////////////////////////////////////// +// VITA49 64 bit time (write only) +//////////////////////////////////////////////// + +#define TIME64_BASE _SR_ADDR(SR_TIME64) + + /*! + * \brief Time 64 flags + * + * 
+   *
+   *    3                   2                   1                       
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-----------------------------------------------------------+-+-+
+   * |                                                           |S|P|
+   * +-----------------------------------------------------------+-+-+
+   *
+   * P - PPS edge selection (0=negedge, 1=posedge, default=0)
+   * S - Source (0=sma, 1=mimo, 0=default)
+   *
+   *
+ */ +typedef struct { + boost::uint32_t secs; // value to set absolute secs to on next PPS + boost::uint32_t ticks; // value to set absolute ticks to on next PPS + boost::uint32_t flags; // flags - see chart above + boost::uint32_t imm; // set immediate (0=latch on next pps, 1=latch immediate, default=0) +} sr_time64_t; + +//pps flags (see above) +#define PPS_FLAG_NEGEDGE (0 << 0) +#define PPS_FLAG_POSEDGE (1 << 0) +#define PPS_FLAG_SMA (0 << 1) +#define PPS_FLAG_MIMO (1 << 1) + +#define TIME64_LATCH_NOW 1 +#define TIME64_LATCH_NEXT_PPS 0 + +///////////////////////////////////////////////// +// DSP TX Regs +//////////////////////////////////////////////// + +#define DSP_TX_BASE _SR_ADDR(SR_TX_DSP) + +typedef struct { + boost::int32_t freq; + boost::uint32_t scale_iq; // {scale_i,scale_q} + boost::uint32_t interp_rate; + boost::uint32_t _padding0; // padding for the tx_mux + // NOT freq, scale, interp + /*! + * \brief output mux configuration. + * + * 
+   *     3                   2                   1                       
+   *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   *  +-------------------------------+-------+-------+-------+-------+
+   *  |                                               | DAC1  |  DAC0 |
+   *  +-------------------------------+-------+-------+-------+-------+
+   * 
+   *  There are N DUCs (1 now) with complex inputs and outputs.
+   *  There are two DACs.
+   * 
+   *  Each 4-bit DACx field specifies the source for the DAC
+   *  Each subfield is coded like this: 
+   * 
+   *     3 2 1 0
+   *    +-------+
+   *    |   N   |
+   *    +-------+
+   * 
+   *  N specifies which DUC output is connected to this DAC.
+   * 
+   *   N   which interp output
+   *  ---  -------------------
+   *   0   DUC 0 I
+   *   1   DUC 0 Q
+   *   2   DUC 1 I
+   *   3   DUC 1 Q
+   *   F   All Zeros
+   *   
+   * The default value is 0x10
+   *
+ */ + boost::uint32_t tx_mux; + +} dsp_tx_regs_t; + +///////////////////////////////////////////////// +// DSP RX Regs +//////////////////////////////////////////////// + +#define DSP_RX_BASE _SR_ADDR(SR_RX_DSP) + +typedef struct { + boost::int32_t freq; + boost::uint32_t scale_iq; // {scale_i,scale_q} + boost::uint32_t decim_rate; + boost::uint32_t dcoffset_i; // Bit 31 high sets fixed offset mode, using lower 14 bits, + // otherwise it is automatic + boost::uint32_t dcoffset_q; // Bit 31 high sets fixed offset mode, using lower 14 bits + + /*! + * \brief input mux configuration. + * + * This determines which ADC (or constant zero) is connected to + * each DDC input. There are N DDCs (1 now). Each has two inputs. + * + * 
+   * Mux value:
+   *
+   *    3                   2                   1                       
+   *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+   * +-------+-------+-------+-------+-------+-------+-------+-------+
+   * |                                                       |Q0 |I0 |
+   * +-------+-------+-------+-------+-------+-------+-------+-------+
+   *
+   * Each 2-bit I field is either 00 (A/D A), 01 (A/D B) or 1X (const zero)
+   * Each 2-bit Q field is either 00 (A/D A), 01 (A/D B) or 1X (const zero)
+   *
+   * The default value is 0x4
+   *
+ */ + boost::uint32_t rx_mux; // called adc_mux in dsp_core_rx.v + +} dsp_rx_regs_t; + //////////////////////////////////////////////// // GPIO, Slave 4 // @@ -35,10 +190,10 @@ typedef struct { } gpio_regs_t; // each 2-bit sel field is layed out this way -#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg -#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic -#define GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric -#define GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric +#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg +#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic +#define GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric +#define GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric /////////////////////////////////////////////////// // ATR Controller, Slave 11 @@ -46,12 +201,12 @@ typedef struct { #define ATR_BASE 0xE400 typedef struct { - boost::uint32_t v[16]; + boost::uint32_t v[16]; } atr_regs_t; -#define ATR_IDLE 0x0 // indicies into v -#define ATR_TX 0x1 -#define ATR_RX 0x2 -#define ATR_FULL 0x3 +#define ATR_IDLE 0x0 // indicies into v +#define ATR_TX 0x1 +#define ATR_RX 0x2 +#define ATR_FULL 0x3 #endif /* INCLUDED_USRP2_REGS_HPP */ -- cgit v1.2.3 From f01b1a394fbf7304aefc0231f500a52db457767a Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Wed, 31 Mar 2010 19:25:22 -0700 Subject: added spi slaves to regs, use std copy for buffs --- firmware/microblaze/apps/txrx.c | 2 +- host/lib/usrp/usrp2/dboard_interface.cpp | 25 +++++++++---------------- host/lib/usrp/usrp2/usrp2_regs.hpp | 13 +++++++++++++ 3 files changed, 23 insertions(+), 17 deletions(-) (limited to 'host/lib/usrp/usrp2/usrp2_regs.hpp') diff --git a/firmware/microblaze/apps/txrx.c b/firmware/microblaze/apps/txrx.c index 430ae2fac..39a503091 100644 --- a/firmware/microblaze/apps/txrx.c +++ b/firmware/microblaze/apps/txrx.c @@ -264,7 +264,7 @@ void handle_udp_ctrl_packet( //transact uint32_t result = spi_transact( (ctrl_data_in->data.spi_args.readback == 0)? SPI_TXONLY : SPI_TXRX, - (ctrl_data_in->data.spi_args.dev == USRP2_DIR_RX)? SPI_SS_RX_DB : SPI_SS_TX_DB, + ctrl_data_in->data.spi_args.dev, data, num_bytes*8, //length in bits (ctrl_data_in->data.spi_args.edge == USRP2_CLK_EDGE_RISE)? SPIF_PUSH_RISE : SPIF_PUSH_FALL | (ctrl_data_in->data.spi_args.edge == USRP2_CLK_EDGE_RISE)? SPIF_LATCH_RISE : SPIF_LATCH_FALL diff --git a/host/lib/usrp/usrp2/dboard_interface.cpp b/host/lib/usrp/usrp2/dboard_interface.cpp index 0bf4fa2e6..f5fe68152 100644 --- a/host/lib/usrp/usrp2/dboard_interface.cpp +++ b/host/lib/usrp/usrp2/dboard_interface.cpp @@ -20,6 +20,7 @@ #include #include #include +#include #include using namespace uhd::usrp; @@ -144,8 +145,8 @@ void usrp2_dboard_interface::set_atr_reg(gpio_bank_t bank, atr_reg_t reg, boost: */ static boost::uint8_t spi_dev_to_otw(dboard_interface::spi_dev_t dev){ switch(dev){ - case uhd::usrp::dboard_interface::SPI_DEV_TX: return USRP2_DIR_TX; - case uhd::usrp::dboard_interface::SPI_DEV_RX: return USRP2_DIR_RX; + case uhd::usrp::dboard_interface::SPI_DEV_TX: return SPI_SS_TX_DB; + case uhd::usrp::dboard_interface::SPI_DEV_RX: return SPI_SS_RX_DB; } throw std::invalid_argument("unknown spi device type"); } @@ -182,9 +183,7 @@ dboard_interface::byte_vector_t usrp2_dboard_interface::transact_spi( ASSERT_THROW(buf.size() <= sizeof(out_data.data.spi_args.data)); //copy in the data - for (size_t i = 0; i < buf.size(); i++){ - out_data.data.spi_args.data[i] = buf[i]; - } + std::copy(buf.begin(), buf.end(), out_data.data.spi_args.data); //send and recv usrp2_ctrl_data_t in_data = _impl->ctrl_send_and_recv(out_data); @@ -192,10 +191,8 @@ dboard_interface::byte_vector_t usrp2_dboard_interface::transact_spi( ASSERT_THROW(in_data.data.spi_args.bytes == buf.size()); //copy out the data - byte_vector_t result; - for (size_t i = 0; i < buf.size(); i++){ - result.push_back(in_data.data.spi_args.data[i]); - } + byte_vector_t result(buf.size()); + std::copy(in_data.data.spi_args.data, in_data.data.spi_args.data + buf.size(), result.begin()); return result; } @@ -213,9 +210,7 @@ void usrp2_dboard_interface::write_i2c(int i2c_addr, const byte_vector_t &buf){ ASSERT_THROW(buf.size() <= sizeof(out_data.data.i2c_args.data)); //copy in the data - for (size_t i = 0; i < buf.size(); i++){ - out_data.data.i2c_args.data[i] = buf[i]; - } + std::copy(buf.begin(), buf.end(), out_data.data.i2c_args.data); //send and recv usrp2_ctrl_data_t in_data = _impl->ctrl_send_and_recv(out_data); @@ -238,10 +233,8 @@ dboard_interface::byte_vector_t usrp2_dboard_interface::read_i2c(int i2c_addr, s ASSERT_THROW(in_data.data.i2c_args.addr = num_bytes); //copy out the data - byte_vector_t result; - for (size_t i = 0; i < num_bytes; i++){ - result.push_back(in_data.data.i2c_args.data[i]); - } + byte_vector_t result(num_bytes); + std::copy(in_data.data.i2c_args.data, in_data.data.i2c_args.data + num_bytes, result.begin()); return result; } diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index 7d868c264..b7fd239a6 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -48,6 +48,19 @@ #define _SR_ADDR(sr) (MISC_OUTPUT_BASE + (sr) * sizeof(uint32_t)) +///////////////////////////////////////////////// +// SPI Slave Constants +//////////////////////////////////////////////// +// Masks for controlling different peripherals +#define SPI_SS_AD9510 1 +#define SPI_SS_AD9777 2 +#define SPI_SS_RX_DAC 4 +#define SPI_SS_RX_ADC 8 +#define SPI_SS_RX_DB 16 +#define SPI_SS_TX_DAC 32 +#define SPI_SS_TX_ADC 64 +#define SPI_SS_TX_DB 128 + ///////////////////////////////////////////////// // VITA49 64 bit time (write only) //////////////////////////////////////////////// -- cgit v1.2.3 From 792fad3afca0eb45fdc3eb27b5d1678c507d4724 Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Thu, 1 Apr 2010 13:30:34 -0700 Subject: use defined constants for the register addresses --- host/lib/usrp/usrp2/dboard_impl.cpp | 5 +- host/lib/usrp/usrp2/dboard_interface.cpp | 15 ++--- host/lib/usrp/usrp2/dsp_impl.cpp | 23 ++----- host/lib/usrp/usrp2/mboard_impl.cpp | 19 +++--- host/lib/usrp/usrp2/usrp2_regs.hpp | 112 ++++++++++++------------------- 5 files changed, 67 insertions(+), 107 deletions(-) (limited to 'host/lib/usrp/usrp2/usrp2_regs.hpp') diff --git a/host/lib/usrp/usrp2/dboard_impl.cpp b/host/lib/usrp/usrp2/dboard_impl.cpp index 86ee52594..29fb32eeb 100644 --- a/host/lib/usrp/usrp2/dboard_impl.cpp +++ b/host/lib/usrp/usrp2/dboard_impl.cpp @@ -20,7 +20,6 @@ #include "usrp2_regs.hpp" #include #include -#include using namespace uhd; using namespace uhd::usrp; @@ -80,7 +79,7 @@ void usrp2_impl::update_rx_mux_config(void){ rx_mux = (((rx_mux >> 0) & 0x3) << 2) | (((rx_mux >> 2) & 0x3) << 0); } - this->poke(offsetof(dsp_rx_regs_t, rx_mux) + DSP_RX_BASE, rx_mux); + this->poke(FR_DSP_RX_MUX, rx_mux); } void usrp2_impl::update_tx_mux_config(void){ @@ -93,7 +92,7 @@ void usrp2_impl::update_tx_mux_config(void){ tx_mux = (((tx_mux >> 0) & 0x1) << 1) | (((tx_mux >> 1) & 0x1) << 0); } - this->poke(offsetof(dsp_tx_regs_t, tx_mux) + DSP_TX_BASE, tx_mux); + this->poke(FR_DSP_TX_MUX, tx_mux); } /*********************************************************************** diff --git a/host/lib/usrp/usrp2/dboard_interface.cpp b/host/lib/usrp/usrp2/dboard_interface.cpp index f5fe68152..4160ad467 100644 --- a/host/lib/usrp/usrp2/dboard_interface.cpp +++ b/host/lib/usrp/usrp2/dboard_interface.cpp @@ -21,7 +21,6 @@ #include #include #include -#include using namespace uhd::usrp; @@ -103,22 +102,22 @@ void usrp2_dboard_interface::set_gpio_ddr(gpio_bank_t bank, boost::uint16_t valu | (boost::uint32_t(value) << shift); //or'ed in the new bits //poke in the value and shadow - _impl->poke(offsetof(gpio_regs_t, ddr) + 0xC800, new_ddr_val); + _impl->poke(FR_GPIO_DDR, new_ddr_val); _ddr_shadow = new_ddr_val; } boost::uint16_t usrp2_dboard_interface::read_gpio(gpio_bank_t bank){ - boost::uint32_t data = _impl->peek(offsetof(gpio_regs_t, io) + 0xC800); + boost::uint32_t data = _impl->peek(FR_GPIO_IO); return boost::uint16_t(data >> bank_to_shift(bank)); } void usrp2_dboard_interface::set_atr_reg(gpio_bank_t bank, atr_reg_t reg, boost::uint16_t value){ //map the atr reg to an offset in register space - static const uhd::dict reg_to_offset = boost::assign::map_list_of - (ATR_REG_IDLE, ATR_IDLE) (ATR_REG_TXONLY, ATR_TX) - (ATR_REG_RXONLY, ATR_RX) (ATR_REG_BOTH, ATR_FULL) + static const uhd::dict reg_to_addr = boost::assign::map_list_of + (ATR_REG_IDLE, FR_ATR_IDLE) (ATR_REG_TXONLY, FR_ATR_TX) + (ATR_REG_RXONLY, FR_ATR_RX) (ATR_REG_BOTH, FR_ATR_FULL) ; - int offset = reg_to_offset[reg]; + ASSERT_THROW(reg_to_addr.has_key(reg)); //ensure a value exists in the shadow if (not _atr_reg_shadows.has_key(reg)) _atr_reg_shadows[reg] = 0; @@ -130,7 +129,7 @@ void usrp2_dboard_interface::set_atr_reg(gpio_bank_t bank, atr_reg_t reg, boost: | (boost::uint32_t(value) << shift); //or'ed in the new bits //poke in the value and shadow - _impl->poke(offsetof(atr_regs_t, v) + 0xE400 + offset, new_atr_val); + _impl->poke(reg_to_addr[reg], new_atr_val); _atr_reg_shadows[reg] = new_atr_val; } diff --git a/host/lib/usrp/usrp2/dsp_impl.cpp b/host/lib/usrp/usrp2/dsp_impl.cpp index 6edfec61a..d50c1ad56 100644 --- a/host/lib/usrp/usrp2/dsp_impl.cpp +++ b/host/lib/usrp/usrp2/dsp_impl.cpp @@ -21,7 +21,6 @@ #include #include #include -#include using namespace uhd; @@ -75,14 +74,11 @@ void usrp2_impl::init_ddc_config(void){ void usrp2_impl::update_ddc_config(void){ //set the decimation - this->poke( - offsetof(dsp_rx_regs_t, decim_rate) + DSP_RX_BASE, _ddc_decim - ); + this->poke(FR_DSP_RX_DECIM_RATE, _ddc_decim); //set the scaling static const boost::int16_t default_rx_scale_iq = 1024; - this->poke( - offsetof(dsp_rx_regs_t, scale_iq) + DSP_RX_BASE, + this->poke(FR_DSP_RX_SCALE_IQ, calculate_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq) ); } @@ -174,8 +170,7 @@ void usrp2_impl::ddc_set(const wax::obj &key, const wax::obj &val){ ASSERT_THROW(new_freq <= get_master_clock_freq()/2.0); ASSERT_THROW(new_freq >= -get_master_clock_freq()/2.0); _ddc_freq = new_freq; //shadow - this->poke( //set the cordic - offsetof(dsp_rx_regs_t, freq) + DSP_RX_BASE, + this->poke(FR_DSP_RX_FREQ, calculate_freq_word_and_update_actual_freq(_ddc_freq, get_master_clock_freq()) ); return; @@ -216,15 +211,10 @@ void usrp2_impl::update_duc_config(void){ boost::int16_t scale = rint((4096*std::pow(2, ceil(log2(interp_cubed))))/(1.65*interp_cubed)); //set the interpolation - this->poke( - offsetof(dsp_tx_regs_t, interp_rate) + DSP_TX_BASE, _ddc_decim - ); + this->poke(FR_DSP_TX_INTERP_RATE, _ddc_decim); //set the scaling - this->poke( - offsetof(dsp_tx_regs_t, scale_iq) + DSP_TX_BASE, - calculate_iq_scale_word(scale, scale) - ); + this->poke(FR_DSP_TX_SCALE_IQ, calculate_iq_scale_word(scale, scale)); } /*********************************************************************** @@ -298,8 +288,7 @@ void usrp2_impl::duc_set(const wax::obj &key, const wax::obj &val){ ASSERT_THROW(new_freq <= get_master_clock_freq()/2.0); ASSERT_THROW(new_freq >= -get_master_clock_freq()/2.0); _duc_freq = new_freq; //shadow - this->poke( //set the cordic - offsetof(dsp_tx_regs_t, freq) + DSP_TX_BASE, + this->poke(FR_DSP_TX_FREQ, calculate_freq_word_and_update_actual_freq(_duc_freq, get_master_clock_freq()) ); return; diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp index eff53c5b2..7b658b22d 100644 --- a/host/lib/usrp/usrp2/mboard_impl.cpp +++ b/host/lib/usrp/usrp2/mboard_impl.cpp @@ -20,7 +20,6 @@ #include #include #include -#include using namespace uhd; @@ -53,32 +52,32 @@ void usrp2_impl::update_clock_config(void){ //translate pps source enums switch(_clock_config.pps_source){ - case clock_config_t::PPS_SMA: pps_flags |= PPS_FLAG_SMA; break; - case clock_config_t::PPS_MIMO: pps_flags |= PPS_FLAG_MIMO; break; + case clock_config_t::PPS_SMA: pps_flags |= FRF_TIME64_PPS_SMA; break; + case clock_config_t::PPS_MIMO: pps_flags |= FRF_TIME64_PPS_MIMO; break; default: throw std::runtime_error("usrp2: unhandled clock configuration pps source"); } //translate pps polarity enums switch(_clock_config.pps_polarity){ - case clock_config_t::PPS_POS: pps_flags |= PPS_FLAG_POSEDGE; break; - case clock_config_t::PPS_NEG: pps_flags |= PPS_FLAG_NEGEDGE; break; + case clock_config_t::PPS_POS: pps_flags |= FRF_TIME64_PPS_POSEDGE; break; + case clock_config_t::PPS_NEG: pps_flags |= FRF_TIME64_PPS_NEGEDGE; break; default: throw std::runtime_error("usrp2: unhandled clock configuration pps polarity"); } //set the pps flags - this->poke(offsetof(sr_time64_t, flags) + TIME64_BASE, pps_flags); + this->poke(FR_TIME64_FLAGS, pps_flags); //TODO clock source ref 10mhz (spi ad9510) } void usrp2_impl::set_time_spec(const time_spec_t &time_spec, bool now){ //set ticks and seconds - this->poke(offsetof(sr_time64_t, secs) + TIME64_BASE, time_spec.secs); - this->poke(offsetof(sr_time64_t, ticks) + TIME64_BASE, time_spec.ticks); + this->poke(FR_TIME64_SECS, time_spec.secs); + this->poke(FR_TIME64_TICKS, time_spec.ticks); //set the register to latch it all in - boost::uint32_t imm_flags = (now)? TIME64_LATCH_NOW : TIME64_LATCH_NEXT_PPS; - this->poke(offsetof(sr_time64_t, imm) + TIME64_BASE, imm_flags); + boost::uint32_t imm_flags = (now)? FRF_TIME64_LATCH_NOW : FRF_TIME64_LATCH_NEXT_PPS; + this->poke(FR_TIME64_IMM, imm_flags); } /*********************************************************************** diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp index b7fd239a6..10545d712 100644 --- a/host/lib/usrp/usrp2/usrp2_regs.hpp +++ b/host/lib/usrp/usrp2/usrp2_regs.hpp @@ -28,10 +28,10 @@ #define MISC_OUTPUT_BASE 0xD400 -#define TX_PROTOCOL_ENGINE_BASE 0xD480 -#define RX_PROTOCOL_ENGINE_BASE 0xD4C0 -#define BUFFER_POOL_CTRL_BASE 0xD500 -#define LAST_SETTING_REG 0xD7FC // last valid setting register +//#define TX_PROTOCOL_ENGINE_BASE 0xD480 +//#define RX_PROTOCOL_ENGINE_BASE 0xD4C0 +//#define BUFFER_POOL_CTRL_BASE 0xD500 +//#define LAST_SETTING_REG 0xD7FC // last valid setting register #define SR_MISC 0 #define SR_TX_PROT_ENG 32 @@ -46,7 +46,7 @@ #define SR_SIMTIMER 198 #define SR_LAST 255 -#define _SR_ADDR(sr) (MISC_OUTPUT_BASE + (sr) * sizeof(uint32_t)) +#define _SR_ADDR(sr) (MISC_OUTPUT_BASE + (sr) * sizeof(boost::uint32_t)) ///////////////////////////////////////////////// // SPI Slave Constants @@ -64,9 +64,6 @@ ///////////////////////////////////////////////// // VITA49 64 bit time (write only) //////////////////////////////////////////////// - -#define TIME64_BASE _SR_ADDR(SR_TIME64) - /*! * \brief Time 64 flags * @@ -83,34 +80,27 @@ * * */ -typedef struct { - boost::uint32_t secs; // value to set absolute secs to on next PPS - boost::uint32_t ticks; // value to set absolute ticks to on next PPS - boost::uint32_t flags; // flags - see chart above - boost::uint32_t imm; // set immediate (0=latch on next pps, 1=latch immediate, default=0) -} sr_time64_t; +#define FR_TIME64_SECS _SR_ADDR(SR_TIME64 + 0) // value to set absolute secs to on next PPS +#define FR_TIME64_TICKS _SR_ADDR(SR_TIME64 + 1) // value to set absolute ticks to on next PPS +#define FR_TIME64_FLAGS _SR_ADDR(SR_TIME64 + 2) // flags - see chart above +#define FR_TIME64_IMM _SR_ADDR(SR_TIME64 + 3) // set immediate (0=latch on next pps, 1=latch immediate, default=0) //pps flags (see above) -#define PPS_FLAG_NEGEDGE (0 << 0) -#define PPS_FLAG_POSEDGE (1 << 0) -#define PPS_FLAG_SMA (0 << 1) -#define PPS_FLAG_MIMO (1 << 1) +#define FRF_TIME64_PPS_NEGEDGE (0 << 0) +#define FRF_TIME64_PPS_POSEDGE (1 << 0) +#define FRF_TIME64_PPS_SMA (0 << 1) +#define FRF_TIME64_PPS_MIMO (1 << 1) -#define TIME64_LATCH_NOW 1 -#define TIME64_LATCH_NEXT_PPS 0 +#define FRF_TIME64_LATCH_NOW 1 +#define FRF_TIME64_LATCH_NEXT_PPS 0 ///////////////////////////////////////////////// // DSP TX Regs //////////////////////////////////////////////// +#define FR_DSP_TX_FREQ _SR_ADDR(SR_TX_DSP + 0) +#define FR_DSP_TX_SCALE_IQ _SR_ADDR(SR_TX_DSP + 1) // {scale_i,scale_q} +#define FR_DSP_TX_INTERP_RATE _SR_ADDR(SR_TX_DSP + 2) -#define DSP_TX_BASE _SR_ADDR(SR_TX_DSP) - -typedef struct { - boost::int32_t freq; - boost::uint32_t scale_iq; // {scale_i,scale_q} - boost::uint32_t interp_rate; - boost::uint32_t _padding0; // padding for the tx_mux - // NOT freq, scale, interp /*! * \brief output mux configuration. * @@ -145,24 +135,17 @@ typedef struct { * The default value is 0x10 * */ - boost::uint32_t tx_mux; - -} dsp_tx_regs_t; +#define FR_DSP_TX_MUX _SR_ADDR(SR_TX_DSP + 4) ///////////////////////////////////////////////// // DSP RX Regs //////////////////////////////////////////////// - -#define DSP_RX_BASE _SR_ADDR(SR_RX_DSP) - -typedef struct { - boost::int32_t freq; - boost::uint32_t scale_iq; // {scale_i,scale_q} - boost::uint32_t decim_rate; - boost::uint32_t dcoffset_i; // Bit 31 high sets fixed offset mode, using lower 14 bits, - // otherwise it is automatic - boost::uint32_t dcoffset_q; // Bit 31 high sets fixed offset mode, using lower 14 bits - +#define FR_DSP_RX_FREQ _SR_ADDR(SR_RX_DSP + 0) +#define FR_DSP_RX_SCALE_IQ _SR_ADDR(SR_RX_DSP + 1) // {scale_i,scale_q} +#define FR_DSP_RX_DECIM_RATE _SR_ADDR(SR_RX_DSP + 2) +#define FR_DSP_RX_DCOFFSET_I _SR_ADDR(SR_RX_DSP + 3) // Bit 31 high sets fixed offset mode, using lower 14 bits, + // otherwise it is automatic +#define FR_DSP_RX_DCOFFSET_Q _SR_ADDR(SR_RX_DSP + 4) // Bit 31 high sets fixed offset mode, using lower 14 bits /*! * \brief input mux configuration. * @@ -184,42 +167,33 @@ typedef struct { * The default value is 0x4 * */ - boost::uint32_t rx_mux; // called adc_mux in dsp_core_rx.v - -} dsp_rx_regs_t; +#define FR_DSP_RX_MUX _SR_ADDR(SR_RX_DSP + 5) // called adc_mux in dsp_core_rx.v //////////////////////////////////////////////// // GPIO, Slave 4 +//////////////////////////////////////////////// // // These go to the daughterboard i/o pins - -#define GPIO_BASE 0xC800 - -typedef struct { - boost::uint32_t io; // tx data in high 16, rx in low 16 - boost::uint32_t ddr; // 32 bits, 1 means output. tx in high 16, rx in low 16 - boost::uint32_t tx_sel; // 16 2-bit fields select which source goes to TX DB - boost::uint32_t rx_sel; // 16 2-bit fields select which source goes to RX DB -} gpio_regs_t; +// +#define _FR_GPIO_ADDR(off) (0xC800 + (off) * sizeof(boost::uint32_t)) +#define FR_GPIO_IO _FR_GPIO_ADDR(0) // tx data in high 16, rx in low 16 +#define FR_GPIO_DDR _FR_GPIO_ADDR(1) // 32 bits, 1 means output. tx in high 16, rx in low 16 +#define FR_GPIO_TX_SEL _FR_GPIO_ADDR(2) // 16 2-bit fields select which source goes to TX DB +#define FR_GPIO_RX_SEL _FR_GPIO_ADDR(3) // 16 2-bit fields select which source goes to RX DB // each 2-bit sel field is layed out this way -#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg -#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic -#define GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric -#define GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric +#define FRF_GPIO_SEL_SW 0 // if pin is an output, set by software in the io reg +#define FRF_GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic +#define FRF_GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from FPGA fabric +#define FRF_GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from FPGA fabric /////////////////////////////////////////////////// // ATR Controller, Slave 11 - -#define ATR_BASE 0xE400 - -typedef struct { - boost::uint32_t v[16]; -} atr_regs_t; - -#define ATR_IDLE 0x0 // indicies into v -#define ATR_TX 0x1 -#define ATR_RX 0x2 -#define ATR_FULL 0x3 +//////////////////////////////////////////////// +#define _FR_ATR_ADDR(off) (0xE400 + (off) * sizeof(boost::uint32_t)) +#define FR_ATR_IDLE _FR_ATR_ADDR(0) // tx data in high 16, rx in low 16 +#define FR_ATR_TX _FR_ATR_ADDR(1) +#define FR_ATR_RX _FR_ATR_ADDR(2) +#define FR_ATR_FULL _FR_ATR_ADDR(3) #endif /* INCLUDED_USRP2_REGS_HPP */ -- cgit v1.2.3