From 11bf23d994fab2a01a27541db959dcc6991b5dd0 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Thu, 17 Feb 2011 15:54:04 -0800
Subject: usrp2: prefix the dsp and ctrl registers with 0 in preparation for
 2nd dsp

---
 host/lib/usrp/usrp2/usrp2_regs.cpp | 36 +++++++++++++++++++-----------------
 1 file changed, 19 insertions(+), 17 deletions(-)

(limited to 'host/lib/usrp/usrp2/usrp2_regs.cpp')

diff --git a/host/lib/usrp/usrp2/usrp2_regs.cpp b/host/lib/usrp/usrp2/usrp2_regs.cpp
index 84907c32e..2159c4276 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.cpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.cpp
@@ -38,8 +38,10 @@ usrp2_regs_t usrp2_get_regs(bool use_n2xx_map) {
   x.sr_udp_sm = 96;
   x.sr_tx_dsp = 208;
   x.sr_tx_ctrl = 224;
-  x.sr_rx_dsp = 160;
-  x.sr_rx_ctrl = 176;
+  x.sr_rx_dsp0 = 160;
+  x.sr_rx_ctrl0 = 176;
+  x.sr_rx_dsp1 = 240;
+  x.sr_rx_ctrl1 = 32;
   x.sr_time64 = 192;
   x.sr_simtimer = 198;
   x.sr_last = 255;
@@ -68,12 +70,12 @@ usrp2_regs_t usrp2_get_regs(bool use_n2xx_map) {
   x.dsp_tx_scale_iq = sr_addr(misc_output_base, x.sr_tx_dsp + 1);
   x.dsp_tx_interp_rate = sr_addr(misc_output_base, x.sr_tx_dsp + 2);
   x.dsp_tx_mux = sr_addr(misc_output_base, x.sr_tx_dsp + 4);
-  x.dsp_rx_freq = sr_addr(misc_output_base, x.sr_rx_dsp + 0);
-  x.dsp_rx_scale_iq = sr_addr(misc_output_base, x.sr_rx_dsp + 1);
-  x.dsp_rx_decim_rate = sr_addr(misc_output_base, x.sr_rx_dsp + 2);
-  x.dsp_rx_dcoffset_i = sr_addr(misc_output_base, x.sr_rx_dsp + 3);
-  x.dsp_rx_dcoffset_q = sr_addr(misc_output_base, x.sr_rx_dsp + 4);
-  x.dsp_rx_mux = sr_addr(misc_output_base, x.sr_rx_dsp + 5);
+  x.dsp0_rx_freq = sr_addr(misc_output_base, x.sr_rx_dsp0 + 0);
+  x.dsp0_rx_scale_iq = sr_addr(misc_output_base, x.sr_rx_dsp0 + 1);
+  x.dsp0_rx_decim_rate = sr_addr(misc_output_base, x.sr_rx_dsp0 + 2);
+  x.dsp0_rx_dcoffset_i = sr_addr(misc_output_base, x.sr_rx_dsp0 + 3);
+  x.dsp0_rx_dcoffset_q = sr_addr(misc_output_base, x.sr_rx_dsp0 + 4);
+  x.dsp0_rx_mux = sr_addr(misc_output_base, x.sr_rx_dsp0 + 5);
   x.gpio_io = gpio_base + 0;
   x.gpio_ddr = gpio_base + 4;
   x.gpio_tx_sel = gpio_base + 8;
@@ -86,15 +88,15 @@ usrp2_regs_t usrp2_get_regs(bool use_n2xx_map) {
   x.atr_inrx_rxside = atr_base + 10;
   x.atr_full_txside = atr_base + 12;
   x.atr_full_rxside = atr_base + 14;
-  x.rx_ctrl_stream_cmd = sr_addr(misc_output_base, x.sr_rx_ctrl + 0);
-  x.rx_ctrl_time_secs = sr_addr(misc_output_base, x.sr_rx_ctrl + 1);
-  x.rx_ctrl_time_ticks = sr_addr(misc_output_base, x.sr_rx_ctrl + 2);
-  x.rx_ctrl_clear_overrun = sr_addr(misc_output_base, x.sr_rx_ctrl + 3);
-  x.rx_ctrl_vrt_header = sr_addr(misc_output_base, x.sr_rx_ctrl + 4);
-  x.rx_ctrl_vrt_stream_id = sr_addr(misc_output_base, x.sr_rx_ctrl + 5);
-  x.rx_ctrl_vrt_trailer = sr_addr(misc_output_base, x.sr_rx_ctrl + 6);
-  x.rx_ctrl_nsamps_per_pkt = sr_addr(misc_output_base, x.sr_rx_ctrl + 7);
-  x.rx_ctrl_nchannels = sr_addr(misc_output_base, x.sr_rx_ctrl + 8);
+  x.rx_ctrl0_stream_cmd = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 0);
+  x.rx_ctrl0_time_secs = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 1);
+  x.rx_ctrl0_time_ticks = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 2);
+  x.rx_ctrl0_clear_overrun = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 3);
+  x.rx_ctrl0_vrt_header = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 4);
+  x.rx_ctrl0_vrt_stream_id = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 5);
+  x.rx_ctrl0_vrt_trailer = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 6);
+  x.rx_ctrl0_nsamps_per_pkt = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 7);
+  x.rx_ctrl0_nchannels = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 8);
   x.tx_ctrl_num_chan = sr_addr(misc_output_base, x.sr_tx_ctrl + 0);
   x.tx_ctrl_clear_state = sr_addr(misc_output_base, x.sr_tx_ctrl + 1);
   x.tx_ctrl_report_sid = sr_addr(misc_output_base, x.sr_tx_ctrl + 2);
-- 
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