From 4b772ff4f3b1e388e150402beaf6567f3ea29e1c Mon Sep 17 00:00:00 2001 From: Josh Blum Date: Sat, 14 May 2011 20:25:52 -0700 Subject: usrp1: correct TX codec rate, it should also read 64e6 when probed We were using clock_rate*2 to simulate a codec rate of 128MHz. This reflected the old gnuradio API, but the rate between FPGA and codec is really 64MHz for both rx and tx directions. --- host/lib/usrp/usrp1/mboard_impl.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'host/lib/usrp/usrp1/mboard_impl.cpp') diff --git a/host/lib/usrp/usrp1/mboard_impl.cpp b/host/lib/usrp/usrp1/mboard_impl.cpp index d6f6832a4..e9108e4f1 100644 --- a/host/lib/usrp/usrp1/mboard_impl.cpp +++ b/host/lib/usrp/usrp1/mboard_impl.cpp @@ -214,8 +214,8 @@ void usrp1_impl::mboard_init(void) // Normal mode with no loopback or Rx counting _iface->poke32(FR_MODE, 0x00000000); _iface->poke32(FR_DEBUG_EN, 0x00000000); - _iface->poke32(FR_RX_SAMPLE_RATE_DIV, 0x00000001); - _iface->poke32(FR_TX_SAMPLE_RATE_DIV, 0x00000003); + _iface->poke32(FR_RX_SAMPLE_RATE_DIV, 0x00000001); //divide by 2 + _iface->poke32(FR_TX_SAMPLE_RATE_DIV, 0x00000001); //divide by 2 _iface->poke32(FR_DC_OFFSET_CL_EN, 0x0000000f); // Reset offset correction registers -- cgit v1.2.3