From 09be0518cee887878f3b070adea25eccc4c06e60 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Wed, 4 May 2011 19:53:01 -0700
Subject: uhd: removed more iostream stuff from usrp* implementations

---
 host/lib/usrp/usrp1/clock_ctrl.cpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'host/lib/usrp/usrp1/clock_ctrl.cpp')

diff --git a/host/lib/usrp/usrp1/clock_ctrl.cpp b/host/lib/usrp/usrp1/clock_ctrl.cpp
index 154e6a316..9edc010dd 100644
--- a/host/lib/usrp/usrp1/clock_ctrl.cpp
+++ b/host/lib/usrp/usrp1/clock_ctrl.cpp
@@ -16,9 +16,9 @@
 //
 
 #include "clock_ctrl.hpp"
+#include <uhd/utils/msg.hpp>
 #include <boost/lexical_cast.hpp>
 #include <boost/format.hpp>
-#include <iostream>
 
 using namespace uhd;
 
@@ -36,14 +36,14 @@ public:
         this->set_master_clock_freq(default_master_clock_rate);
         try{
             if (not _iface->mb_eeprom["mcr"].empty()){
-                std::cout << "Read FPGA clock rate from EEPROM setting." << std::endl;
+                UHD_MSG(status) << "Read FPGA clock rate from EEPROM setting." << std::endl;
                 const double master_clock_rate = boost::lexical_cast<double>(_iface->mb_eeprom["mcr"]);
-                std::cout << boost::format("Initializing FPGA clock to %fMHz...") % (master_clock_rate/1e6) << std::endl;
+                UHD_MSG(status) << boost::format("Initializing FPGA clock to %fMHz...") % (master_clock_rate/1e6) << std::endl;
                 this->set_master_clock_freq(master_clock_rate);
             }
         }
         catch(const std::exception &e){
-            std::cerr << "Error setting FPGA clock rate from EEPROM: " << e.what() << std::endl;
+            UHD_MSG(error) << "Error setting FPGA clock rate from EEPROM: " << e.what() << std::endl;
         }
     }
 
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