From c03506fedd75a7fbad242d2be06123a187e66277 Mon Sep 17 00:00:00 2001
From: Ashish Chaudhari <ashish@ettus.com>
Date: Fri, 19 Feb 2016 17:38:08 -0800
Subject: dboard: Made dboard class dtors virtual

- Interface and all base classes have virtual destructors
- Wrapped UBX dtor in UHD_SAFE_CALL
---
 host/lib/usrp/dboard/db_ubx.cpp | 48 ++++++++++++++++++++++-------------------
 1 file changed, 26 insertions(+), 22 deletions(-)

(limited to 'host/lib/usrp/dboard/db_ubx.cpp')

diff --git a/host/lib/usrp/dboard/db_ubx.cpp b/host/lib/usrp/dboard/db_ubx.cpp
index 91f1f51eb..88c8d93c9 100644
--- a/host/lib/usrp/dboard/db_ubx.cpp
+++ b/host/lib/usrp/dboard/db_ubx.cpp
@@ -29,6 +29,7 @@
 #include <uhd/utils/log.hpp>
 #include <uhd/utils/msg.hpp>
 #include <uhd/utils/static.hpp>
+#include <uhd/utils/safe_call.hpp>
 #include <boost/assign/list_of.hpp>
 #include <boost/shared_ptr.hpp>
 #include <boost/math/special_functions/round.hpp>
@@ -477,31 +478,34 @@ public:
             .set(-8);
     }
 
-    ~ubx_xcvr(void)
+    virtual ~ubx_xcvr(void)
     {
-        // Shutdown synthesizers
-        _txlo1->shutdown();
-        _txlo2->shutdown();
-        _rxlo1->shutdown();
-        _rxlo2->shutdown();
+        UHD_SAFE_CALL
+        (
+            // Shutdown synthesizers
+            _txlo1->shutdown();
+            _txlo2->shutdown();
+            _rxlo1->shutdown();
+            _rxlo2->shutdown();
 
-        // Reset CPLD values
-        _cpld_reg.value = 0;
-        write_cpld_reg();
+            // Reset CPLD values
+            _cpld_reg.value = 0;
+            write_cpld_reg();
 
-        // Reset GPIO values
-        set_gpio_field(TX_GAIN, 0);
-        set_gpio_field(CPLD_RST_N, 0);
-        set_gpio_field(RX_ANT, 1);
-        set_gpio_field(TX_EN_N, 1);
-        set_gpio_field(RX_EN_N, 1);
-        set_gpio_field(SPI_ADDR, 0x7);
-        set_gpio_field(RX_GAIN, 0);
-        set_gpio_field(TXLO1_SYNC, 0);
-        set_gpio_field(TXLO2_SYNC, 0);
-        set_gpio_field(RXLO1_SYNC, 0);
-        set_gpio_field(RXLO1_SYNC, 0);
-        write_gpio();
+            // Reset GPIO values
+            set_gpio_field(TX_GAIN, 0);
+            set_gpio_field(CPLD_RST_N, 0);
+            set_gpio_field(RX_ANT, 1);
+            set_gpio_field(TX_EN_N, 1);
+            set_gpio_field(RX_EN_N, 1);
+            set_gpio_field(SPI_ADDR, 0x7);
+            set_gpio_field(RX_GAIN, 0);
+            set_gpio_field(TXLO1_SYNC, 0);
+            set_gpio_field(TXLO2_SYNC, 0);
+            set_gpio_field(RXLO1_SYNC, 0);
+            set_gpio_field(RXLO1_SYNC, 0);
+            write_gpio();
+        )
     }
 
 private:
-- 
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