From c7274790a0b8a812d731320c2b7711efa2e1daa7 Mon Sep 17 00:00:00 2001 From: Ashish Chaudhari Date: Fri, 1 Aug 2014 13:14:56 -0700 Subject: b200: Moved AD9361 driver to host - Switched to FPGA SPI engine - Moved firmware AD9361 driver to UHD - Bumped FW compat to 5, FPGA compat to 4 - Known Issue: AD9361 SPI rate is too slow --- host/lib/usrp/b200/b200_regs.hpp | 1 + 1 file changed, 1 insertion(+) (limited to 'host/lib/usrp/b200/b200_regs.hpp') diff --git a/host/lib/usrp/b200/b200_regs.hpp b/host/lib/usrp/b200/b200_regs.hpp index c64066b27..2f4373409 100644 --- a/host/lib/usrp/b200/b200_regs.hpp +++ b/host/lib/usrp/b200/b200_regs.hpp @@ -52,6 +52,7 @@ localparam RB64_TIME_PPS = 16; localparam RB64_CODEC_READBACK = 24; //pll constants +static const int AD9361_SLAVENO = (1 << 0); static const int ADF4001_SLAVENO = (1 << 1); static const double ADF4001_SPI_RATE = 10e3; //slow for large time constant on spi lines -- cgit v1.2.3