From db6f3a2d7aabdd0eaa1021ac174edd3cbb77be55 Mon Sep 17 00:00:00 2001
From: Ashish Chaudhari <ashish@ettus.com>
Date: Fri, 1 Aug 2014 16:29:34 -0700
Subject: b200: Added variable rate SPI core for AD9361 and ADF4001

- Added b200_local_spi core that adjusts the divider when talking to the two chips
- AD9361 rate is 1MHz and ADF4001 rate is 10kHz
---
 host/lib/usrp/b200/b200_cores.cpp | 83 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 83 insertions(+)
 create mode 100644 host/lib/usrp/b200/b200_cores.cpp

(limited to 'host/lib/usrp/b200/b200_cores.cpp')

diff --git a/host/lib/usrp/b200/b200_cores.cpp b/host/lib/usrp/b200/b200_cores.cpp
new file mode 100644
index 000000000..19e637ef4
--- /dev/null
+++ b/host/lib/usrp/b200/b200_cores.cpp
@@ -0,0 +1,83 @@
+//
+// Copyright 2013-2014 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+#include "b200_cores.hpp"
+#include "b200_regs.hpp"
+#include "b200_impl.hpp"
+
+b200_local_spi_core::b200_local_spi_core(
+    uhd::wb_iface::sptr iface,
+    perif_t default_perif) :
+    _spi_core(spi_core_3000::make(iface, TOREG(SR_CORE_SPI), RB32_CORE_SPI)),
+    _current_perif(default_perif),
+    _last_perif(default_perif)
+{
+    change_perif(default_perif);
+}
+
+boost::uint32_t b200_local_spi_core::transact_spi(
+    int which_slave,
+    const uhd::spi_config_t &config,
+    boost::uint32_t data,
+    size_t num_bits,
+    bool readback)
+{
+    boost::mutex::scoped_lock lock(_mutex);
+    return _spi_core->transact_spi(which_slave, config, data, num_bits, readback);
+}
+
+void b200_local_spi_core::change_perif(perif_t perif)
+{
+    boost::mutex::scoped_lock lock(_mutex);
+    _last_perif = _current_perif;
+    _current_perif = perif;
+
+    switch (_current_perif) {
+        case CODEC:
+            _spi_core->set_divider(B200_BUS_CLOCK_RATE/AD9361_SPI_RATE);
+            break;
+        case PLL:
+            _spi_core->set_divider(B200_BUS_CLOCK_RATE/ADF4001_SPI_RATE);
+            break;
+    }
+}
+
+void b200_local_spi_core::restore_perif()
+{
+    change_perif(_last_perif);
+}
+
+b200_ref_pll_ctrl::b200_ref_pll_ctrl(b200_local_spi_core::sptr spi) :
+    uhd::usrp::adf4001_ctrl(spi, ADF4001_SLAVENO),
+    _spi(spi)
+{
+}
+
+void b200_ref_pll_ctrl::set_lock_to_ext_ref(bool external)
+{
+    _spi->change_perif(b200_local_spi_core::PLL);
+    adf4001_ctrl::set_lock_to_ext_ref(external);
+    _spi->restore_perif();
+}
+
+
+b200_local_spi_core::sptr b200_local_spi_core::make(
+    uhd::wb_iface::sptr iface, b200_local_spi_core::perif_t default_perif)
+{
+    return sptr(new b200_local_spi_core(iface, default_perif));
+}
+
-- 
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