From 699870d7dec67b43c08e55fcc1d4e159a337c49a Mon Sep 17 00:00:00 2001 From: michael-west Date: Thu, 9 Dec 2021 16:22:28 -0800 Subject: RFNoC: Fix DSP frequency accuracy The host code was calculating and programming a 32-bit value for the DSP frequency, but the DDS modules in the FPGA only use the upper 24-bits. This led to inaccurate frequency values being returned. This change corrects the resolution of the value on the host side so an accurate value is returned. Signed-off-by: michael-west --- host/lib/rfnoc/ddc_block_control.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'host/lib/rfnoc/ddc_block_control.cpp') diff --git a/host/lib/rfnoc/ddc_block_control.cpp b/host/lib/rfnoc/ddc_block_control.cpp index df606f11b..12e89961d 100644 --- a/host/lib/rfnoc/ddc_block_control.cpp +++ b/host/lib/rfnoc/ddc_block_control.cpp @@ -541,10 +541,15 @@ private: double _set_freq( const double requested_freq, const double dds_rate, const size_t chan) { + static int freq_word_width = 24; double actual_freq; int32_t freq_word; std::tie(actual_freq, freq_word) = - get_freq_and_freq_word(requested_freq, dds_rate); + get_freq_and_freq_word(requested_freq, dds_rate, freq_word_width); + + // Only the upper 24 bits of the SR_FREQ_ADDR register are used, so shift the word + freq_word <<= (32 - freq_word_width); + _ddc_reg_iface.poke32( SR_FREQ_ADDR, uint32_t(freq_word), chan, get_command_time(chan)); return actual_freq; -- cgit v1.2.3