From 6d3765605262016a80f71e36357f749ea35cbe5a Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Tue, 8 Jun 2021 19:40:46 -0500 Subject: fpga: x400: Add support for X410 motherboard FPGA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Andrew Moch Co-authored-by: Daniel Jepson Co-authored-by: Javier Valenzuela Co-authored-by: Joerg Hofrichter Co-authored-by: Kumaran Subramoniam Co-authored-by: Max Köhler Co-authored-by: Michael Auchter Co-authored-by: Paul Butler Co-authored-by: Wade Fife Co-authored-by: Hector Rubio --- fpga/usrp3/top/x400/rf/common/sync_wrapper.v | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 fpga/usrp3/top/x400/rf/common/sync_wrapper.v (limited to 'fpga/usrp3/top/x400/rf/common/sync_wrapper.v') diff --git a/fpga/usrp3/top/x400/rf/common/sync_wrapper.v b/fpga/usrp3/top/x400/rf/common/sync_wrapper.v new file mode 100644 index 000000000..797d19d5f --- /dev/null +++ b/fpga/usrp3/top/x400/rf/common/sync_wrapper.v @@ -0,0 +1,43 @@ +// +// Copyright 2021 Ettus Research, a National Instruments Brand +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// Module: sync_wrapper +// +// Description: +// +// As the original synchronizer component has port signal names that are +// incompatible with VHDL (in, out), this modules provides an an interface to +// instantiate the synchronizer block in VHDL. +// + +`default_nettype none + +module sync_wrapper #( + parameter WIDTH = 1, + parameter STAGES = 2, + parameter INITIAL_VAL = 0, + parameter FALSE_PATH_TO_IN = 1 +)( + input wire clk, + input wire rst, + input wire [WIDTH-1:0] signal_in, + output wire [WIDTH-1:0] signal_out +); + +synchronizer #( + .WIDTH (WIDTH), + .STAGES (STAGES), + .INITIAL_VAL (INITIAL_VAL), + .FALSE_PATH_TO_IN (FALSE_PATH_TO_IN) +) synchronizer_i ( + .clk (clk), + .rst (rst), + .in (signal_in), + .out (signal_out) +); + +endmodule //sync_wrapper + +`default_nettype wire -- cgit v1.2.3