From e1ce4565dbc7336ee806adce7c087bda4fcc77ae Mon Sep 17 00:00:00 2001 From: Humberto Jimenez Date: Wed, 27 Oct 2021 14:54:46 -0500 Subject: fpga: x400: Refactor CPLDs build process This commit refactors the X410's CPLDs build process to make it similar to other FPGA targets within the repo. The new process relies on basic Quartus build utilities. Additionally, this commit adds support for an alternative MAX10 CPLD for the motherboard CPLD implementation. Both previous (10M04) and new variant (10M08) are supported concurrently. The images package mapping is updated to reflect these changes. --- fpga/usrp3/top/x400/cpld/Makefile | 148 ++++--- fpga/usrp3/top/x400/cpld/Makefile.cpld.inc | 51 +++ fpga/usrp3/top/x400/cpld/ip/Makefile.inc | 22 ++ fpga/usrp3/top/x400/cpld/ip/clkctrl/.gitignore | 2 +- fpga/usrp3/top/x400/cpld/ip/clkctrl/Makefile.inc | 16 + fpga/usrp3/top/x400/cpld/ip/flash/.gitignore | 3 - .../top/x400/cpld/ip/flash/on_chip_flash.qsys | 90 ----- .../top/x400/cpld/ip/on_chip_flash/.gitignore | 3 + .../top/x400/cpld/ip/on_chip_flash/Makefile.inc | 16 + .../x400/cpld/ip/on_chip_flash/on_chip_flash.qsys | 90 +++++ fpga/usrp3/top/x400/cpld/mb_cpld.qpf | 30 -- fpga/usrp3/top/x400/cpld/mb_cpld.qsf | 431 -------------------- fpga/usrp3/top/x400/cpld/mb_cpld.v | 2 +- fpga/usrp3/top/x400/cpld/quartus/mb_cpld.qpf | 30 ++ fpga/usrp3/top/x400/cpld/quartus/mb_cpld.qsf | 432 +++++++++++++++++++++ .../usrp3/top/x400/cpld/quartus/ps_cs_analysis.tcl | 32 ++ .../usrp3/top/x400/cpld/quartus/raw_conversion.cof | 39 ++ fpga/usrp3/top/x400/cpld/raw_conversion.cof | 39 -- fpga/usrp3/top/x400/cpld/reconfig_engine.v | 58 ++- .../top/x400/cpld/regmap/constants_regmap_utils.vh | 2 +- .../top/x400/cpld/regmap/reconfig_regmap_utils.vh | 11 +- .../usrp3/top/x400/cpld/scripts/ps_cs_analysis.tcl | 32 -- 22 files changed, 871 insertions(+), 708 deletions(-) create mode 100644 fpga/usrp3/top/x400/cpld/Makefile.cpld.inc create mode 100644 fpga/usrp3/top/x400/cpld/ip/Makefile.inc create mode 100644 fpga/usrp3/top/x400/cpld/ip/clkctrl/Makefile.inc delete mode 100644 fpga/usrp3/top/x400/cpld/ip/flash/.gitignore delete mode 100644 fpga/usrp3/top/x400/cpld/ip/flash/on_chip_flash.qsys create mode 100644 fpga/usrp3/top/x400/cpld/ip/on_chip_flash/.gitignore create mode 100644 fpga/usrp3/top/x400/cpld/ip/on_chip_flash/Makefile.inc create mode 100644 fpga/usrp3/top/x400/cpld/ip/on_chip_flash/on_chip_flash.qsys delete mode 100644 fpga/usrp3/top/x400/cpld/mb_cpld.qpf delete mode 100644 fpga/usrp3/top/x400/cpld/mb_cpld.qsf create mode 100644 fpga/usrp3/top/x400/cpld/quartus/mb_cpld.qpf create mode 100644 fpga/usrp3/top/x400/cpld/quartus/mb_cpld.qsf create mode 100644 fpga/usrp3/top/x400/cpld/quartus/ps_cs_analysis.tcl create mode 100644 fpga/usrp3/top/x400/cpld/quartus/raw_conversion.cof delete mode 100644 fpga/usrp3/top/x400/cpld/raw_conversion.cof delete mode 100644 fpga/usrp3/top/x400/cpld/scripts/ps_cs_analysis.tcl (limited to 'fpga/usrp3/top/x400/cpld') diff --git a/fpga/usrp3/top/x400/cpld/Makefile b/fpga/usrp3/top/x400/cpld/Makefile index 68c6c8908..56ae3cd82 100644 --- a/fpga/usrp3/top/x400/cpld/Makefile +++ b/fpga/usrp3/top/x400/cpld/Makefile @@ -4,74 +4,94 @@ # SPDX-License-Identifier: LGPL-3.0-or-later # -GIT_HASH = $(shell ../../../tools/scripts/git-hash.sh) - -build: ip - @echo -ne "\n---- Make: Synthesis ...\n\n"; - @quartus_map mb_cpld --verilog_macro="GIT_HASH=32'h$(GIT_HASH)"; - @echo -ne "\n---- Make: Partition Merge ...\n\n"; - @quartus_cdb mb_cpld --merge=on --incremental_compilation_import - @echo -ne "\n\n---- Make: Implementation ...\n\n"; - @quartus_fit mb_cpld; - @echo -ne "\n\n---- Make: Analyzing timing ...\n\n"; - @quartus_sta mb_cpld; - @# grep for unconstrained path warning - @grep "332102" output_files/mb_cpld.sta.rpt; \ - if [ $$? -eq 0 ]; then false; else true; fi - @# grep for timing closure critical warning - @grep "332148" output_files/mb_cpld.sta.rpt; \ - if [ $$? -eq 0 ]; then false; else true; fi - @# expect no warnings - @grep -iw "warning" output_files/mb_cpld.sta.rpt; \ - if [ $$? -eq 0 ]; then false; else true; fi - @# expect no critical warning except "review power analyzer report file" - @grep -i "critical warning" output_files/* | grep -v 16562; \ - if [ $$? -eq 0 ]; then false; else true; fi - @# PS chip select analysis - @quartus_sta -t scripts/ps_cs_analysis.tcl - @echo -ne "\n\n---- Make: Generating bitfile...\n\n"; - @quartus_asm mb_cpld; - @echo -ne "\n\n---- Make: Converting bitfile to svf format (ISP enabled)...\n\n"; - @quartus_cpf --convert \ - --frequency 10.0MHz \ - --voltage 2.5 \ - --operation p \ - ./output_files/mb_cpld.pof ./output_files/mb_cpld_isp_on.svf -o background_programming=on; - @echo -ne "\n\n---- Make: Converting bitfile to svf format (ISP disabled)...\n\n"; - @quartus_cpf --convert \ - --frequency 10.0MHz \ - --voltage 2.5 \ - --operation p \ - ./output_files/mb_cpld.pof ./output_files/mb_cpld_isp_off.svf; - @echo -ne "\n\n---- Make: Converting bitfile to rdp format...\n\n"; - @quartus_cpf -c raw_conversion.cof - @echo -ne "\n\n---- Make: Copy final files...\n\n"; - @mkdir -p build - @cp output_files/mb_cpld.pof build/usrp_x410_cpld.pof - @cp output_files/mb_cpld_isp_off.svf build/usrp_x410_cpld_isp_off.svf - @cp output_files/mb_cpld_isp_on.svf build/usrp_x410_cpld.svf - @cp output_files/mb_cpld_converted_cfm0_auto.rpd build/usrp_x410_cpld.rpd - @echo -ne "\n\n---- Make: MB CPLD ready!\n"; - @echo -ne " Use build/usrp_x410_cpld.pof via JTAG programmer or\n" - @echo -ne " build/usrp_x410_cpld.svf (ISP on) via PS JTAG-engine (background programming) or\n" - @echo -ne " build/usrp_x410_cpld.rpd via reconfig engine or\n" - @echo -ne " build/usrp_x410_cpld_isp_off.svf via JTAG test points (initial programming)\n" - -clean: - @echo -ne "\nCleaning MB CPLD...\n"; - @git clean -Xdf +# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target +##------------------- +##USRP X410 CPLD Help +##------------------- +##Usage: +## make +## +##Output: +## build//usrp_x410_cpld.pof: Bitstream to use with JTAG programmer +## build//usrp_x410_cpld.svf: Bitstream to use with PS JTAG engine (background programming) +## build//usrp_x410_cpld.rpd: Bitstream to use via reconfig engine +## build//usrp_x410_cpld_isp_off.svf: Bitstream to use with JTAG test points (initial programming) + +# Definitions +10M04_ID = "10M04SAU169I7G" +10M08_ID = "10M08SAU169I7G" + +# Target specific variables +X410_CPLD_10M04: DEFS = VARIANT_`echo $(10M04_ID) | cut -c1-5`=1 +X410_CPLD_10M08: DEFS = VARIANT_`echo $(10M08_ID) | cut -c1-5`=1 + +TARGET = bin +TOP ?= mb_cpld + +# quartus_build($1=Device, $2=Definitions) +quartus_build = make -f Makefile.cpld.inc $(TARGET) NAME=$@ ARCH="MAX10" PART_ID="$1" $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" POST_STA_TCL="ps_cs_analysis.tcl" + +# quartus_ip($1=Device, $2=Definitions) +quartus_ip = make -f Makefile.cpld.inc quar_ip NAME=$@ ARCH="MAX10" PART_ID="$1" $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" + +# post_build($1=Artifact Name) +ifeq ($(TARGET),bin) + post_build = @\ + mkdir -p build/; \ + echo "Exporting bitstream files..."; \ + cp build-$@/output_files/$(TOP).pof build/$(1).pof; \ + cp build-$@/output_files/$(TOP)_isp_off.svf build/$(1)_isp_off.svf; \ + cp build-$@/output_files/$(TOP)_isp_on.svf build/$(1).svf; \ + cp build-$@/output_files/$(TOP)_converted_cfm0_auto.rpd build/$(1).rpd; \ + echo -ne "\n\n---- Make: MB CPLD ready!\n"; \ + echo -ne " Use build/$(1).pof via JTAG programmer or\n"; \ + echo -ne " build/$(1).svf (ISP on) via PS JTAG-engine (background programming) or\n"; \ + echo -ne " build/$(1).rpd via reconfig engine or\n"; \ + echo -ne " build/$(1)_isp_off.svf via JTAG test points (initial programming)\n"; +else + post_build = @echo "Skipping bitfile export." +endif -QSYS_PATH=$(subst \,/,$(QSYS_ROOTDIR)) +## +##Supported Targets +##----------------- -ip: ip/flash/on_chip_flash/simulation/on_chip_flash.v \ - ip/clkctrl/clkctrl/simulation/clkctrl.v +all: X410_CPLD_10M04 X410_CPLD_10M08 ##(Default target) -ip/flash/on_chip_flash/simulation/on_chip_flash.v: - $(QSYS_PATH)/qsys-generate ip/flash/on_chip_flash.qsys --simulation=VERILOG +##X410_CPLD_10M04: Motherboard CPLD targeted to 10M04SAU169I7G. +X410_CPLD_10M04: + $(call quartus_build,$(10M04_ID),$(DEFS)) + $(call post_build,"usrp_x410_cpld_`echo $(10M04_ID) | cut -c1-5 | tr A-Z a-z`") + +##X410_CPLD_10M08: Motherboard CPLD targeted to 10M08SAU169I7G. +X410_CPLD_10M08: + $(call quartus_build,$(10M08_ID),$(DEFS)) + $(call post_build,"usrp_x410_cpld_`echo $(10M08_ID) | cut -c1-5 | tr A-Z a-z`") + + +X410_CPLD_IP: ##Build IPs only, needed for simulation. + @# Building only X410_CPLD_10M04 IP + $(call quartus_ip,$(10M04_ID),$(DEFS)) + +clean: ##Clean up all target build outputs. + @echo -ne "\nCleaning targets and git repo...\n"; + @rm -rf build-X410_CPLD* + @rm -rf build + @git clean -Xdf + +cleanall: ##Clean up all target and ip build outputs. + @echo -ne "\nCleaning targets, IP, and git repo...\n"; + @rm -rf build-X410_CPLD* + @rm -rf build + @rm -rf build-ip + @git clean -Xdf -ip/clkctrl/clkctrl/simulation/clkctrl.v: - $(QSYS_PATH)/qsys-generate ip/clkctrl/clkctrl.qsys --simulation=VERILOG +help: ##Show this help message. + @grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//' -all: build +## +##Supported Options +##----------------- +## .PHONY: all build clean ip diff --git a/fpga/usrp3/top/x400/cpld/Makefile.cpld.inc b/fpga/usrp3/top/x400/cpld/Makefile.cpld.inc new file mode 100644 index 000000000..bc3c6c97c --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/Makefile.cpld.inc @@ -0,0 +1,51 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +################################################## +# Project Setup +################################################## +# TOP_MODULE = +# NAME = +# PART_ID = +# ARCH = + +################################################## +# Include other makefiles +################################################## + +PROJECT_DIR = $(abspath .) +BASE_DIR = $(abspath ../..) +IP_DIR = $(abspath ./ip) +include $(BASE_DIR)/../tools/make/quartus_design_builder.mak + +# Include IP directory +include $(IP_DIR)/Makefile.inc + +# Define VERILOG_DEFS for macros definition +VERILOG_DEFS=$(EXTRA_DEFS) $(GIT_HASH_VERILOG_DEF) + +bin: .prereqs + $(call BUILD_QUARTUS_DESIGN,$(TOP_MODULE),$(ARCH),$(PART_ID),$(PROJECT_DIR),$(BUILD_DIR),$(POST_TCL_SCRIPT),1) + @\ + pushd $(BUILD_DIR); \ + echo "Converting bitfile to svf format (ISP enabled)..."; \ + quartus_cpf --convert \ + --frequency 10.0MHz \ + --voltage 2.5 \ + --operation p \ + output_files/$(TOP_MODULE).pof output_files/$(TOP_MODULE)_isp_on.svf -o background_programming=on; \ + echo "Converting bitfile to svf format (ISP disabled)..."; \ + quartus_cpf --convert \ + --frequency 10.0MHz \ + --voltage 2.5 \ + --operation p \ + output_files/$(TOP_MODULE).pof output_files/$(TOP_MODULE)_isp_off.svf; \ + echo "Converting bitfile to rpd format..."; \ + quartus_cpf -c raw_conversion.cof; \ + popd; + +quar_ip: .prereqs ip + @echo "IP Build DONE ..." diff --git a/fpga/usrp3/top/x400/cpld/ip/Makefile.inc b/fpga/usrp3/top/x400/cpld/ip/Makefile.inc new file mode 100644 index 000000000..1d238d83c --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/ip/Makefile.inc @@ -0,0 +1,22 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(IP_DIR)/on_chip_flash/Makefile.inc +include $(IP_DIR)/clkctrl/Makefile.inc + +IP_SRCS = \ +$(IP_ON_CHIP_FLASH_SRCS) \ +$(IP_CLKCTRL_SRCS) + + +IP_OUTPUTS = \ +$(IP_ON_CHIP_FLASH_OUTS) \ +$(IP_CLKCTRL_OUTS) + + +ip: $(IP_OUTPUTS) + +.PHONY: ip diff --git a/fpga/usrp3/top/x400/cpld/ip/clkctrl/.gitignore b/fpga/usrp3/top/x400/cpld/ip/clkctrl/.gitignore index 9776d9b81..87dce88a7 100644 --- a/fpga/usrp3/top/x400/cpld/ip/clkctrl/.gitignore +++ b/fpga/usrp3/top/x400/cpld/ip/clkctrl/.gitignore @@ -1,3 +1,3 @@ # generate files clkctrl/ -clkctrl.sopcinfo \ No newline at end of file +clkctrl.sopcinfo diff --git a/fpga/usrp3/top/x400/cpld/ip/clkctrl/Makefile.inc b/fpga/usrp3/top/x400/cpld/ip/clkctrl/Makefile.inc new file mode 100644 index 000000000..2015c6976 --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/ip/clkctrl/Makefile.inc @@ -0,0 +1,16 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/quartus_ip_builder.mak + +IP_CLKCTRL_SRCS = \ +$(IP_BUILD_DIR)/clkctrl/clkctrl.qsys + +IP_CLKCTRL_OUTS = \ +$(IP_BUILD_DIR)/clkctrl/clkctrl.sopcinfo + +$(IP_CLKCTRL_SRCS) $(IP_CLKCTRL_OUTS) : $(IP_DIR)/clkctrl/clkctrl.qsys + $(call BUILD_QUARTUS_IP,clkctrl,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/x400/cpld/ip/flash/.gitignore b/fpga/usrp3/top/x400/cpld/ip/flash/.gitignore deleted file mode 100644 index 585bc126d..000000000 --- a/fpga/usrp3/top/x400/cpld/ip/flash/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -# generate files -on_chip_flash/ -on_chip_flash.sopcinfo diff --git a/fpga/usrp3/top/x400/cpld/ip/flash/on_chip_flash.qsys b/fpga/usrp3/top/x400/cpld/ip/flash/on_chip_flash.qsys deleted file mode 100644 index 4cbe8726a..000000000 --- a/fpga/usrp3/top/x400/cpld/ip/flash/on_chip_flash.qsys +++ /dev/null @@ -1,90 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Single Compressed Image - Internal Configuration - - - - - - Read and write,Read and write,Read and write,Read and write,Read and write - $${FILENAME}_onchip_flash_0 - - altera_onchip_flash.hex - altera_onchip_flash.dat - - - - - - - diff --git a/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/.gitignore b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/.gitignore new file mode 100644 index 000000000..585bc126d --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/.gitignore @@ -0,0 +1,3 @@ +# generate files +on_chip_flash/ +on_chip_flash.sopcinfo diff --git a/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/Makefile.inc b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/Makefile.inc new file mode 100644 index 000000000..fcd8528e6 --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/Makefile.inc @@ -0,0 +1,16 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# + +include $(TOOLS_DIR)/make/quartus_ip_builder.mak + +IP_ON_CHIP_FLASH_SRCS = \ +$(IP_BUILD_DIR)/on_chip_flash/on_chip_flash.qsys + +IP_ON_CHIP_FLASH_OUTS = \ +$(IP_BUILD_DIR)/on_chip_flash/on_chip_flash.sopcinfo + +$(IP_ON_CHIP_FLASH_SRCS) $(IP_ON_CHIP_FLASH_OUTS) : $(IP_DIR)/on_chip_flash/on_chip_flash.qsys + $(call BUILD_QUARTUS_IP,on_chip_flash,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR)) diff --git a/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/on_chip_flash.qsys b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/on_chip_flash.qsys new file mode 100644 index 000000000..4cbe8726a --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/ip/on_chip_flash/on_chip_flash.qsys @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Single Compressed Image + Internal Configuration + + + + + + Read and write,Read and write,Read and write,Read and write,Read and write + $${FILENAME}_onchip_flash_0 + + altera_onchip_flash.hex + altera_onchip_flash.dat + + + + + + + diff --git a/fpga/usrp3/top/x400/cpld/mb_cpld.qpf b/fpga/usrp3/top/x400/cpld/mb_cpld.qpf deleted file mode 100644 index 0e34c0ac5..000000000 --- a/fpga/usrp3/top/x400/cpld/mb_cpld.qpf +++ /dev/null @@ -1,30 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2018 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition -# Date created = 13:40:17 August 15, 2019 -# -# -------------------------------------------------------------------------- # - -QUARTUS_VERSION = "18.1" -DATE = "13:40:17 August 15, 2019" - -# Revisions - -PROJECT_REVISION = "mb_cpld" diff --git a/fpga/usrp3/top/x400/cpld/mb_cpld.qsf b/fpga/usrp3/top/x400/cpld/mb_cpld.qsf deleted file mode 100644 index 47ab072ce..000000000 --- a/fpga/usrp3/top/x400/cpld/mb_cpld.qsf +++ /dev/null @@ -1,431 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2018 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition -# Date created = 12:02:17 February 20, 2019 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# TopCpld_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus Prime software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - - -#-------------------------------------------------------------------------- -# Project properties/settings -#-------------------------------------------------------------------------- -set_global_assignment -name FAMILY "MAX 10" -set_global_assignment -name DEVICE 10M04SAU169I7G -set_global_assignment -name TOP_LEVEL_ENTITY mb_cpld -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:02:17 FEBRUARY 20, 2019" -set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Standard Edition" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON -set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" -set_global_assignment -name ENABLE_OCT_DONE OFF -set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF -set_global_assignment -name ENABLE_JTAG_PIN_SHARING ON -set_global_assignment -name GENERATE_SVF_FILE OFF -set_global_assignment -name USE_CONFIGURATION_DEVICE OFF -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top - -set_global_assignment -name NUM_PARALLEL_PROCESSORS 2 - -#-------------------------------------------------------------------------- -# Pin constraints -#-------------------------------------------------------------------------- - -# Clocking. -#------------------------------------------ - -# CPLD's PLL reference clock. -set_location_assignment PIN_H6 -to PLL_REF_CLK -set_location_assignment PIN_G5 -to "PLL_REF_CLK(n)" -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to PLL_REF_CLK - -# Reliable clock (100 MHz). -set_location_assignment PIN_H4 -to CLK_100 -set_location_assignment PIN_H5 -to "CLK_100(n)" -set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to CLK_100 - -# Power supply clocks. -set_location_assignment PIN_H8 -to PWR_SUPPLY_CLK_CORE -set_location_assignment PIN_H9 -to PWR_SUPPLY_CLK_DDR4_S -set_location_assignment PIN_G12 -to PWR_SUPPLY_CLK_DDR4_N -set_location_assignment PIN_L13 -to PWR_SUPPLY_CLK_0P9V -set_location_assignment PIN_G13 -to PWR_SUPPLY_CLK_1P8V -set_location_assignment PIN_K10 -to PWR_SUPPLY_CLK_2P5V -set_location_assignment PIN_J10 -to PWR_SUPPLY_CLK_3P3V -set_location_assignment PIN_L12 -to PWR_SUPPLY_CLK_3P6V -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_0P9V -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_1P8V -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_2P5V -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_3P3V -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_3P6V -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_CORE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_DDR4_N -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_DDR4_S - -# Oscillator power supply -set_location_assignment PIN_L2 -to PWR_EN_5V_OSC_100 -set_location_assignment PIN_N2 -to PWR_EN_5V_OSC_122_88 -set_instance_assignment -name IO_STANDARD "2.5 V" -to PWR_EN_5V_OSC_100 -set_instance_assignment -name IO_STANDARD "2.5 V" -to PWR_EN_5V_OSC_122_88 - - -# Interfaces from/to RFSoC. -#------------------------------------------ - -# PL SPI slave interface. -set_location_assignment PIN_G2 -to PL_CPLD_SCLK -set_location_assignment PIN_F5 -to PL_CPLD_MOSI -set_location_assignment PIN_F6 -to PL_CPLD_MISO -set_location_assignment PIN_G1 -to PL_CPLD_CS_N[0] -set_location_assignment PIN_G4 -to PL_CPLD_CS_N[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_SCLK -set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_MOSI -set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_MISO -set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_CS_N[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_CS_N[1] - -# IRQ to PL. -set_location_assignment PIN_F4 -to PL_CPLD_IRQ -set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_IRQ - -# PS SPI slave interface. -set_location_assignment PIN_E3 -to PS_CPLD_SCLK -set_location_assignment PIN_E1 -to PS_CPLD_MOSI -set_location_assignment PIN_F1 -to PS_CPLD_MISO -set_location_assignment PIN_B1 -to PS_CPLD_CS_N[0] -set_location_assignment PIN_C1 -to PS_CPLD_CS_N[1] -set_location_assignment PIN_E4 -to PS_CPLD_CS_N[2] -set_location_assignment PIN_D1 -to PS_CPLD_CS_N[3] -set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_SCLK -set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_MOSI -set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_MISO -set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_CS_N[0] -set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_CS_N[1] -set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_CS_N[2] -set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_CS_N[3] - - -# PL Interfaces to/from motherboard. -#------------------------------------------ - -# White Rabbit DAC SPI master interface. -set_location_assignment PIN_A12 -to CLK_DB_SCLK -set_location_assignment PIN_B13 -to CLK_DB_MOSI -set_location_assignment PIN_D12 -to CLK_DB_MISO -set_location_assignment PIN_D9 -to CLK_DB_CS_N -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLK_DB_SCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLK_DB_MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLK_DB_MISO -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLK_DB_CS_N - -# iPASS interfaces. -set_location_assignment PIN_A6 -to IPASS_SCL[0] -set_location_assignment PIN_H2 -to IPASS_SCL[1] -set_location_assignment PIN_A7 -to IPASS_SDA[0] -set_location_assignment PIN_H3 -to IPASS_SDA[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to IPASS_SCL[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to IPASS_SCL[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to IPASS_SDA[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to IPASS_SDA[1] - -set_location_assignment PIN_B11 -to IPASS_PRESENT_N[0] -set_location_assignment PIN_F8 -to IPASS_PRESENT_N[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_PRESENT_N[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_PRESENT_N[1] - -# QSFP LEDs. -set_location_assignment PIN_E12 -to QSFP0_LED_ACTIVE[0] -set_location_assignment PIN_F12 -to QSFP0_LED_ACTIVE[1] -set_location_assignment PIN_E9 -to QSFP0_LED_ACTIVE[2] -set_location_assignment PIN_J1 -to QSFP0_LED_ACTIVE[3] -set_location_assignment PIN_F10 -to QSFP0_LED_LINK[0] -set_location_assignment PIN_F9 -to QSFP0_LED_LINK[1] -set_location_assignment PIN_N11 -to QSFP0_LED_LINK[2] -set_location_assignment PIN_D13 -to QSFP0_LED_LINK[3] -set_location_assignment PIN_M1 -to QSFP1_LED_ACTIVE[0] -set_location_assignment PIN_N3 -to QSFP1_LED_ACTIVE[1] -set_location_assignment PIN_L3 -to QSFP1_LED_ACTIVE[2] -set_location_assignment PIN_K2 -to QSFP1_LED_ACTIVE[3] -set_location_assignment PIN_M2 -to QSFP1_LED_LINK[0] -set_location_assignment PIN_M3 -to QSFP1_LED_LINK[1] -set_location_assignment PIN_K1 -to QSFP1_LED_LINK[2] -set_location_assignment PIN_L1 -to QSFP1_LED_LINK[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_ACTIVE[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_ACTIVE[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_ACTIVE[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP0_LED_ACTIVE[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_LINK[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_LINK[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_LINK[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_LINK[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_ACTIVE[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_ACTIVE[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_ACTIVE[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_ACTIVE[3] -set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_LINK[0] -set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_LINK[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_LINK[2] -set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_LINK[3] - -# DIO direction control. -set_location_assignment PIN_N12 -to DIO_DIRECTION_A[0] -set_location_assignment PIN_N10 -to DIO_DIRECTION_A[1] -set_location_assignment PIN_N9 -to DIO_DIRECTION_A[2] -set_location_assignment PIN_M4 -to DIO_DIRECTION_A[3] -set_location_assignment PIN_M5 -to DIO_DIRECTION_A[4] -set_location_assignment PIN_N4 -to DIO_DIRECTION_A[5] -set_location_assignment PIN_N5 -to DIO_DIRECTION_A[6] -set_location_assignment PIN_N7 -to DIO_DIRECTION_A[7] -set_location_assignment PIN_N8 -to DIO_DIRECTION_A[8] -set_location_assignment PIN_M8 -to DIO_DIRECTION_A[9] -set_location_assignment PIN_M9 -to DIO_DIRECTION_A[10] -set_location_assignment PIN_M13 -to DIO_DIRECTION_A[11] -set_location_assignment PIN_L5 -to DIO_DIRECTION_B[0] -set_location_assignment PIN_L4 -to DIO_DIRECTION_B[1] -set_location_assignment PIN_K5 -to DIO_DIRECTION_B[2] -set_location_assignment PIN_J5 -to DIO_DIRECTION_B[3] -set_location_assignment PIN_N6 -to DIO_DIRECTION_B[4] -set_location_assignment PIN_M7 -to DIO_DIRECTION_B[5] -set_location_assignment PIN_J6 -to DIO_DIRECTION_B[6] -set_location_assignment PIN_K6 -to DIO_DIRECTION_B[7] -set_location_assignment PIN_J7 -to DIO_DIRECTION_B[8] -set_location_assignment PIN_K7 -to DIO_DIRECTION_B[9] -set_location_assignment PIN_M12 -to DIO_DIRECTION_B[10] -set_location_assignment PIN_M11 -to DIO_DIRECTION_B[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[11] - - -# PS Interfaces to/from motherboard. -#------------------------------------------ - -# LMK04832 SPI master interface. -set_location_assignment PIN_J9 -to LMK32_SCLK -set_location_assignment PIN_H13 -to LMK32_MOSI -set_location_assignment PIN_L11 -to LMK32_MISO -set_location_assignment PIN_J13 -to LMK32_CS_N -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK32_SCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK32_MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK32_MISO -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK32_CS_N - -# TPM 2.0 SPI master interface. -set_location_assignment PIN_D11 -to TPM_SCLK -set_location_assignment PIN_E10 -to TPM_MOSI -set_location_assignment PIN_C13 -to TPM_MISO -set_location_assignment PIN_L10 -to TPM_CS_N -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_SCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_MISO -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_CS_N - -# Phase DAC SPI master interface. -set_location_assignment PIN_K8 -to PHASE_DAC_SCLK -set_location_assignment PIN_J8 -to PHASE_DAC_MOSI -set_location_assignment PIN_M10 -to PHASE_DAC_CS_N -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_SCLK -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_MOSI -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_CS_N - -# Daughterboards' JTAG master interfaces. -set_location_assignment PIN_J12 -to DB_JTAG_TCK[0] -set_location_assignment PIN_G9 -to DB_JTAG_TCK[1] -set_location_assignment PIN_K12 -to DB_JTAG_TDI[0] -set_location_assignment PIN_E13 -to DB_JTAG_TDI[1] -set_location_assignment PIN_H10 -to DB_JTAG_TDO[0] -set_location_assignment PIN_F13 -to DB_JTAG_TDO[1] -set_location_assignment PIN_K11 -to DB_JTAG_TMS[0] -set_location_assignment PIN_G10 -to DB_JTAG_TMS[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TCK[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TCK[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDI[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDI[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDO[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDO[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TMS[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TMS[1] - -# Daughterboards' Calibration EEPROM SPI interfaces. -set_location_assignment PIN_C9 -to DB_CALEEPROM_CS_N[0] -set_location_assignment PIN_B9 -to DB_CALEEPROM_MISO[0] -set_location_assignment PIN_B10 -to DB_CALEEPROM_MOSI[0] -set_location_assignment PIN_A10 -to DB_CALEEPROM_SCLK[0] - -set_location_assignment PIN_B5 -to DB_CALEEPROM_MOSI[1] -set_location_assignment PIN_B6 -to DB_CALEEPROM_SCLK[1] -set_location_assignment PIN_B4 -to DB_CALEEPROM_MISO[1] -set_location_assignment PIN_B3 -to DB_CALEEPROM_CS_N[1] - -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_CS_N[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MISO[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MOSI[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_SCLK[0] - -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MOSI[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_SCLK[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MISO[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_CS_N[1] - -# Daughterboards' Control interfaces. -set_location_assignment PIN_C10 -to DB_CTRL_SCLK[0] -set_location_assignment PIN_A9 -to DB_CTRL_MISO[0] -set_location_assignment PIN_A8 -to DB_ARST[0] -set_location_assignment PIN_A11 -to DB_CTRL_CS_N[0] -set_location_assignment PIN_E8 -to DB_CTRL_MOSI[0] -set_location_assignment PIN_D8 -to DB_REF_CLK[0] - -set_location_assignment PIN_A3 -to DB_REF_CLK[1] -set_location_assignment PIN_A4 -to DB_CTRL_MISO[1] -set_location_assignment PIN_D6 -to DB_CTRL_CS_N[1] -set_location_assignment PIN_E6 -to DB_CTRL_SCLK[1] -set_location_assignment PIN_A5 -to DB_CTRL_MOSI[1] -set_location_assignment PIN_B2 -to DB_ARST[1] - -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_SCLK[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MISO[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_ARST[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_CS_N[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MOSI[0] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_REF_CLK[0] - -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_REF_CLK[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MISO[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_CS_N[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_SCLK[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MOSI[1] -set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_ARST[1] - - -# Miscellaneous. -#------------------------------------------ - -# Power supply clocks switch. -set_location_assignment PIN_J2 -to PS_CLK_ON_CPLD -set_instance_assignment -name IO_STANDARD "2.5 V" -to PS_CLK_ON_CPLD - -# iPASS misc. -set_location_assignment PIN_B12 -to IPASS_POWER_DISABLE -set_location_assignment PIN_C11 -to IPASS_POWER_EN_FAULT[0] -set_location_assignment PIN_C12 -to IPASS_POWER_EN_FAULT[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_POWER_DISABLE -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_POWER_EN_FAULT[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_POWER_EN_FAULT[1] - -# PCIe reset to FPGA. -set_location_assignment PIN_A2 -to PCIE_RESET -set_instance_assignment -name IO_STANDARD "1.8 V" -to PCIE_RESET - -# TPM reset. -set_location_assignment PIN_K13 -to TPM_RESET_n -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_RESET_n - -# File list. -set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 -set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE" -set_global_assignment -name EN_USER_IO_WEAK_PULLUP OFF -set_global_assignment -name EN_SPI_IO_WEAK_PULLUP OFF - -set_global_assignment -name VHDL_FILE ip/cmi/PcieCmiWrapper.vhd -set_global_assignment -name VHDL_FILE ip/cmi/PcieCmi.vhd -set_global_assignment -name QSYS_FILE ip/clkctrl/clkctrl.qsys -set_global_assignment -name QSYS_FILE ip/flash/on_chip_flash.qsys -set_global_assignment -name SDC_FILE db_spi_shared_constants.sdc -set_global_assignment -name SDC_FILE mb_cpld.sdc -set_global_assignment -name VERILOG_FILE reconfig_engine.v -set_global_assignment -name VERILOG_FILE mb_cpld.v -set_global_assignment -name VERILOG_FILE ctrlport_to_spi.v -set_global_assignment -name VERILOG_FILE ctrlport_to_jtag.v -set_global_assignment -name VERILOG_FILE pl_cpld_regs.v -set_global_assignment -name VERILOG_FILE pwr_supply_clk_gen.v -set_global_assignment -name VERILOG_FILE ps_cpld_regs.v -set_global_assignment -name VERILOG_FILE reset_generator.v -set_global_assignment -name VERILOG_FILE spi_slave_to_ctrlport_master.v -set_global_assignment -name VERILOG_FILE spi_slave.v -set_global_assignment -name QIP_FILE ip/pll/pll.qip -set_global_assignment -name VERILOG_FILE ../../../lib/control/synchronizer_impl.v -set_global_assignment -name VERILOG_FILE ../../../lib/control/synchronizer.v -set_global_assignment -name VERILOG_FILE ../../../lib/rfnoc/utils/ctrlport_splitter.v -set_global_assignment -name VERILOG_FILE ../../../lib/rfnoc/utils/ctrlport_terminator.v -set_global_assignment -name VERILOG_FILE ../../../lib/wb_spi/rtl/verilog/spi_top.v -set_global_assignment -name VERILOG_FILE ../../../lib/wb_spi/rtl/verilog/spi_shift.v -set_global_assignment -name VERILOG_FILE ../../../lib/wb_spi/rtl/verilog/spi_defines.v -set_global_assignment -name VERILOG_FILE ../../../lib/wb_spi/rtl/verilog/spi_clgen.v -set_global_assignment -name VERILOG_FILE ../../../lib/control/pulse_synchronizer.v -set_global_assignment -name VERILOG_FILE ../../../lib/control/handshake.v -set_global_assignment -name VHDL_FILE ../../../lib/vivado_ipi/axi_bitq/bitq_fsm.vhd -set_global_assignment -name VHDL_FILE ../../../lib/vivado_ipi/axi_bitq/axi_bitq.vhd -set_global_assignment -name QIP_FILE ip/oddr/oddr.qip -set_global_assignment -name SOURCE_FILE db/mb_cpld.cmp.rdb -set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id "PcieCmi:PcieCmix" -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id "PcieCmi:PcieCmix" -set_global_assignment -name PARTITION_COLOR 52377 -section_id "PcieCmi:PcieCmix" -set_global_assignment -name PARTITION_IMPORT_FILE ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix" -set_global_assignment -name PARTITION_LAST_IMPORTED_FILE ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix" -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -set_instance_assignment -name PARTITION_HIERARCHY pciec_5b6b1 -to "PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix" -section_id "PcieCmi:PcieCmix" \ No newline at end of file diff --git a/fpga/usrp3/top/x400/cpld/mb_cpld.v b/fpga/usrp3/top/x400/cpld/mb_cpld.v index 4ea5dc574..2e709acd9 100644 --- a/fpga/usrp3/top/x400/cpld/mb_cpld.v +++ b/fpga/usrp3/top/x400/cpld/mb_cpld.v @@ -1025,7 +1025,7 @@ endmodule // // // -// +// // // // diff --git a/fpga/usrp3/top/x400/cpld/quartus/mb_cpld.qpf b/fpga/usrp3/top/x400/cpld/quartus/mb_cpld.qpf new file mode 100644 index 000000000..0e34c0ac5 --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/quartus/mb_cpld.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# Date created = 13:40:17 August 15, 2019 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.1" +DATE = "13:40:17 August 15, 2019" + +# Revisions + +PROJECT_REVISION = "mb_cpld" diff --git a/fpga/usrp3/top/x400/cpld/quartus/mb_cpld.qsf b/fpga/usrp3/top/x400/cpld/quartus/mb_cpld.qsf new file mode 100644 index 000000000..001391cfc --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/quartus/mb_cpld.qsf @@ -0,0 +1,432 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# Date created = 12:02:17 February 20, 2019 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# TopCpld_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + + +#-------------------------------------------------------------------------- +# Project properties/settings +#-------------------------------------------------------------------------- +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M04SAU169I7G +set_global_assignment -name TOP_LEVEL_ENTITY mb_cpld +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:02:17 FEBRUARY 20, 2019" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Standard Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF +set_global_assignment -name ENABLE_JTAG_PIN_SHARING ON +set_global_assignment -name GENERATE_SVF_FILE OFF +set_global_assignment -name USE_CONFIGURATION_DEVICE OFF +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + +set_global_assignment -name NUM_PARALLEL_PROCESSORS 2 + +#-------------------------------------------------------------------------- +# Pin constraints +#-------------------------------------------------------------------------- + +# Clocking. +#------------------------------------------ + +# CPLD's PLL reference clock. +set_location_assignment PIN_H6 -to PLL_REF_CLK +set_location_assignment PIN_G5 -to "PLL_REF_CLK(n)" +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to PLL_REF_CLK + +# Reliable clock (100 MHz). +set_location_assignment PIN_H4 -to CLK_100 +set_location_assignment PIN_H5 -to "CLK_100(n)" +set_instance_assignment -name IO_STANDARD "DIFFERENTIAL LVPECL" -to CLK_100 + +# Power supply clocks. +set_location_assignment PIN_H8 -to PWR_SUPPLY_CLK_CORE +set_location_assignment PIN_H9 -to PWR_SUPPLY_CLK_DDR4_S +set_location_assignment PIN_G12 -to PWR_SUPPLY_CLK_DDR4_N +set_location_assignment PIN_L13 -to PWR_SUPPLY_CLK_0P9V +set_location_assignment PIN_G13 -to PWR_SUPPLY_CLK_1P8V +set_location_assignment PIN_K10 -to PWR_SUPPLY_CLK_2P5V +set_location_assignment PIN_J10 -to PWR_SUPPLY_CLK_3P3V +set_location_assignment PIN_L12 -to PWR_SUPPLY_CLK_3P6V +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_0P9V +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_1P8V +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_2P5V +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_3P3V +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_3P6V +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_CORE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_DDR4_N +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PWR_SUPPLY_CLK_DDR4_S + +# Oscillator power supply +set_location_assignment PIN_L2 -to PWR_EN_5V_OSC_100 +set_location_assignment PIN_N2 -to PWR_EN_5V_OSC_122_88 +set_instance_assignment -name IO_STANDARD "2.5 V" -to PWR_EN_5V_OSC_100 +set_instance_assignment -name IO_STANDARD "2.5 V" -to PWR_EN_5V_OSC_122_88 + + +# Interfaces from/to RFSoC. +#------------------------------------------ + +# PL SPI slave interface. +set_location_assignment PIN_G2 -to PL_CPLD_SCLK +set_location_assignment PIN_F5 -to PL_CPLD_MOSI +set_location_assignment PIN_F6 -to PL_CPLD_MISO +set_location_assignment PIN_G1 -to PL_CPLD_CS_N[0] +set_location_assignment PIN_G4 -to PL_CPLD_CS_N[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_SCLK +set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_MOSI +set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_MISO +set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_CS_N[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_CS_N[1] + +# IRQ to PL. +set_location_assignment PIN_F4 -to PL_CPLD_IRQ +set_instance_assignment -name IO_STANDARD "1.8 V" -to PL_CPLD_IRQ + +# PS SPI slave interface. +set_location_assignment PIN_E3 -to PS_CPLD_SCLK +set_location_assignment PIN_E1 -to PS_CPLD_MOSI +set_location_assignment PIN_F1 -to PS_CPLD_MISO +set_location_assignment PIN_B1 -to PS_CPLD_CS_N[0] +set_location_assignment PIN_C1 -to PS_CPLD_CS_N[1] +set_location_assignment PIN_E4 -to PS_CPLD_CS_N[2] +set_location_assignment PIN_D1 -to PS_CPLD_CS_N[3] +set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_SCLK +set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_MOSI +set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_MISO +set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_CS_N[0] +set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_CS_N[1] +set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_CS_N[2] +set_instance_assignment -name IO_STANDARD "1.8-V" -to PS_CPLD_CS_N[3] + + +# PL Interfaces to/from motherboard. +#------------------------------------------ + +# White Rabbit DAC SPI master interface. +set_location_assignment PIN_A12 -to CLK_DB_SCLK +set_location_assignment PIN_B13 -to CLK_DB_MOSI +set_location_assignment PIN_D12 -to CLK_DB_MISO +set_location_assignment PIN_D9 -to CLK_DB_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLK_DB_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLK_DB_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLK_DB_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CLK_DB_CS_N + +# iPASS interfaces. +set_location_assignment PIN_A6 -to IPASS_SCL[0] +set_location_assignment PIN_H2 -to IPASS_SCL[1] +set_location_assignment PIN_A7 -to IPASS_SDA[0] +set_location_assignment PIN_H3 -to IPASS_SDA[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to IPASS_SCL[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to IPASS_SCL[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to IPASS_SDA[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to IPASS_SDA[1] + +set_location_assignment PIN_B11 -to IPASS_PRESENT_N[0] +set_location_assignment PIN_F8 -to IPASS_PRESENT_N[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_PRESENT_N[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_PRESENT_N[1] + +# QSFP LEDs. +set_location_assignment PIN_E12 -to QSFP0_LED_ACTIVE[0] +set_location_assignment PIN_F12 -to QSFP0_LED_ACTIVE[1] +set_location_assignment PIN_E9 -to QSFP0_LED_ACTIVE[2] +set_location_assignment PIN_J1 -to QSFP0_LED_ACTIVE[3] +set_location_assignment PIN_F10 -to QSFP0_LED_LINK[0] +set_location_assignment PIN_F9 -to QSFP0_LED_LINK[1] +set_location_assignment PIN_N11 -to QSFP0_LED_LINK[2] +set_location_assignment PIN_D13 -to QSFP0_LED_LINK[3] +set_location_assignment PIN_M1 -to QSFP1_LED_ACTIVE[0] +set_location_assignment PIN_N3 -to QSFP1_LED_ACTIVE[1] +set_location_assignment PIN_L3 -to QSFP1_LED_ACTIVE[2] +set_location_assignment PIN_K2 -to QSFP1_LED_ACTIVE[3] +set_location_assignment PIN_M2 -to QSFP1_LED_LINK[0] +set_location_assignment PIN_M3 -to QSFP1_LED_LINK[1] +set_location_assignment PIN_K1 -to QSFP1_LED_LINK[2] +set_location_assignment PIN_L1 -to QSFP1_LED_LINK[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_ACTIVE[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_ACTIVE[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_ACTIVE[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP0_LED_ACTIVE[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_LINK[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_LINK[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_LINK[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to QSFP0_LED_LINK[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_ACTIVE[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_ACTIVE[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_ACTIVE[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_ACTIVE[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_LINK[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_LINK[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_LINK[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to QSFP1_LED_LINK[3] + +# DIO direction control. +set_location_assignment PIN_N12 -to DIO_DIRECTION_A[0] +set_location_assignment PIN_N10 -to DIO_DIRECTION_A[1] +set_location_assignment PIN_N9 -to DIO_DIRECTION_A[2] +set_location_assignment PIN_M4 -to DIO_DIRECTION_A[3] +set_location_assignment PIN_M5 -to DIO_DIRECTION_A[4] +set_location_assignment PIN_N4 -to DIO_DIRECTION_A[5] +set_location_assignment PIN_N5 -to DIO_DIRECTION_A[6] +set_location_assignment PIN_N7 -to DIO_DIRECTION_A[7] +set_location_assignment PIN_N8 -to DIO_DIRECTION_A[8] +set_location_assignment PIN_M8 -to DIO_DIRECTION_A[9] +set_location_assignment PIN_M9 -to DIO_DIRECTION_A[10] +set_location_assignment PIN_M13 -to DIO_DIRECTION_A[11] +set_location_assignment PIN_L5 -to DIO_DIRECTION_B[0] +set_location_assignment PIN_L4 -to DIO_DIRECTION_B[1] +set_location_assignment PIN_K5 -to DIO_DIRECTION_B[2] +set_location_assignment PIN_J5 -to DIO_DIRECTION_B[3] +set_location_assignment PIN_N6 -to DIO_DIRECTION_B[4] +set_location_assignment PIN_M7 -to DIO_DIRECTION_B[5] +set_location_assignment PIN_J6 -to DIO_DIRECTION_B[6] +set_location_assignment PIN_K6 -to DIO_DIRECTION_B[7] +set_location_assignment PIN_J7 -to DIO_DIRECTION_B[8] +set_location_assignment PIN_K7 -to DIO_DIRECTION_B[9] +set_location_assignment PIN_M12 -to DIO_DIRECTION_B[10] +set_location_assignment PIN_M11 -to DIO_DIRECTION_B[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_A[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DIO_DIRECTION_B[11] + + +# PS Interfaces to/from motherboard. +#------------------------------------------ + +# LMK04832 SPI master interface. +set_location_assignment PIN_J9 -to LMK32_SCLK +set_location_assignment PIN_H13 -to LMK32_MOSI +set_location_assignment PIN_L11 -to LMK32_MISO +set_location_assignment PIN_J13 -to LMK32_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK32_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK32_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK32_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to LMK32_CS_N + +# TPM 2.0 SPI master interface. +set_location_assignment PIN_D11 -to TPM_SCLK +set_location_assignment PIN_E10 -to TPM_MOSI +set_location_assignment PIN_C13 -to TPM_MISO +set_location_assignment PIN_L10 -to TPM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_MISO +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_CS_N + +# Phase DAC SPI master interface. +set_location_assignment PIN_K8 -to PHASE_DAC_SCLK +set_location_assignment PIN_J8 -to PHASE_DAC_MOSI +set_location_assignment PIN_M10 -to PHASE_DAC_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_MOSI +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PHASE_DAC_CS_N + +# Daughterboards' JTAG master interfaces. +set_location_assignment PIN_J12 -to DB_JTAG_TCK[0] +set_location_assignment PIN_G9 -to DB_JTAG_TCK[1] +set_location_assignment PIN_K12 -to DB_JTAG_TDI[0] +set_location_assignment PIN_E13 -to DB_JTAG_TDI[1] +set_location_assignment PIN_H10 -to DB_JTAG_TDO[0] +set_location_assignment PIN_F13 -to DB_JTAG_TDO[1] +set_location_assignment PIN_K11 -to DB_JTAG_TMS[0] +set_location_assignment PIN_G10 -to DB_JTAG_TMS[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TCK[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TCK[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDI[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDI[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TDO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TMS[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to DB_JTAG_TMS[1] + +# Daughterboards' Calibration EEPROM SPI interfaces. +set_location_assignment PIN_C9 -to DB_CALEEPROM_CS_N[0] +set_location_assignment PIN_B9 -to DB_CALEEPROM_MISO[0] +set_location_assignment PIN_B10 -to DB_CALEEPROM_MOSI[0] +set_location_assignment PIN_A10 -to DB_CALEEPROM_SCLK[0] + +set_location_assignment PIN_B5 -to DB_CALEEPROM_MOSI[1] +set_location_assignment PIN_B6 -to DB_CALEEPROM_SCLK[1] +set_location_assignment PIN_B4 -to DB_CALEEPROM_MISO[1] +set_location_assignment PIN_B3 -to DB_CALEEPROM_CS_N[1] + +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_CS_N[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MISO[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MOSI[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_SCLK[0] + +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MOSI[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_SCLK[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_MISO[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CALEEPROM_CS_N[1] + +# Daughterboards' Control interfaces. +set_location_assignment PIN_C10 -to DB_CTRL_SCLK[0] +set_location_assignment PIN_A9 -to DB_CTRL_MISO[0] +set_location_assignment PIN_A8 -to DB_ARST[0] +set_location_assignment PIN_A11 -to DB_CTRL_CS_N[0] +set_location_assignment PIN_E8 -to DB_CTRL_MOSI[0] +set_location_assignment PIN_D8 -to DB_REF_CLK[0] + +set_location_assignment PIN_A3 -to DB_REF_CLK[1] +set_location_assignment PIN_A4 -to DB_CTRL_MISO[1] +set_location_assignment PIN_D6 -to DB_CTRL_CS_N[1] +set_location_assignment PIN_E6 -to DB_CTRL_SCLK[1] +set_location_assignment PIN_A5 -to DB_CTRL_MOSI[1] +set_location_assignment PIN_B2 -to DB_ARST[1] + +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_SCLK[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MISO[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_ARST[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_CS_N[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MOSI[0] +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_REF_CLK[0] + +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_REF_CLK[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MISO[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_CS_N[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_SCLK[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_CTRL_MOSI[1] +set_instance_assignment -name IO_STANDARD "1.8 V" -to DB_ARST[1] + + +# Miscellaneous. +#------------------------------------------ + +# Power supply clocks switch. +set_location_assignment PIN_J2 -to PS_CLK_ON_CPLD +set_instance_assignment -name IO_STANDARD "2.5 V" -to PS_CLK_ON_CPLD + +# iPASS misc. +set_location_assignment PIN_B12 -to IPASS_POWER_DISABLE +set_location_assignment PIN_C11 -to IPASS_POWER_EN_FAULT[0] +set_location_assignment PIN_C12 -to IPASS_POWER_EN_FAULT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_POWER_DISABLE +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_POWER_EN_FAULT[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to IPASS_POWER_EN_FAULT[1] + +# PCIe reset to FPGA. +set_location_assignment PIN_A2 -to PCIE_RESET +set_instance_assignment -name IO_STANDARD "1.8 V" -to PCIE_RESET + +# TPM reset. +set_location_assignment PIN_K13 -to TPM_RESET_n +set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to TPM_RESET_n + +# File list. +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "SINGLE COMP IMAGE" +set_global_assignment -name EN_USER_IO_WEAK_PULLUP OFF +set_global_assignment -name EN_SPI_IO_WEAK_PULLUP OFF + +set_global_assignment -name VHDL_FILE ../ip/cmi/PcieCmiWrapper.vhd +set_global_assignment -name VHDL_FILE ../ip/cmi/PcieCmi.vhd +set_global_assignment -name QSYS_FILE ../ip/clkctrl/clkctrl.qsys +set_global_assignment -name QSYS_FILE ../ip/on_chip_flash/on_chip_flash.qsys +set_global_assignment -name SDC_FILE ../db_spi_shared_constants.sdc +set_global_assignment -name SDC_FILE ../mb_cpld.sdc +set_global_assignment -name VERILOG_FILE ../reconfig_engine.v +set_global_assignment -name VERILOG_FILE ../mb_cpld.v +set_global_assignment -name VERILOG_FILE ../ctrlport_to_spi.v +set_global_assignment -name VERILOG_FILE ../ctrlport_to_jtag.v +set_global_assignment -name VERILOG_FILE ../pl_cpld_regs.v +set_global_assignment -name VERILOG_FILE ../pwr_supply_clk_gen.v +set_global_assignment -name VERILOG_FILE ../ps_cpld_regs.v +set_global_assignment -name VERILOG_FILE ../ps_power_regs.v +set_global_assignment -name VERILOG_FILE ../reset_generator.v +set_global_assignment -name VERILOG_FILE ../spi_slave_to_ctrlport_master.v +set_global_assignment -name VERILOG_FILE ../spi_slave.v +set_global_assignment -name QIP_FILE ../ip/pll/pll.qip +set_global_assignment -name VERILOG_FILE ../../../../lib/control/synchronizer_impl.v +set_global_assignment -name VERILOG_FILE ../../../../lib/control/synchronizer.v +set_global_assignment -name VERILOG_FILE ../../../../lib/rfnoc/utils/ctrlport_splitter.v +set_global_assignment -name VERILOG_FILE ../../../../lib/rfnoc/utils/ctrlport_terminator.v +set_global_assignment -name VERILOG_FILE ../../../../lib/wb_spi/rtl/verilog/spi_top.v +set_global_assignment -name VERILOG_FILE ../../../../lib/wb_spi/rtl/verilog/spi_shift.v +set_global_assignment -name VERILOG_FILE ../../../../lib/wb_spi/rtl/verilog/spi_defines.v +set_global_assignment -name VERILOG_FILE ../../../../lib/wb_spi/rtl/verilog/spi_clgen.v +set_global_assignment -name VERILOG_FILE ../../../../lib/control/pulse_synchronizer.v +set_global_assignment -name VERILOG_FILE ../../../../lib/control/handshake.v +set_global_assignment -name VHDL_FILE ../../../../lib/vivado_ipi/axi_bitq/bitq_fsm.vhd +set_global_assignment -name VHDL_FILE ../../../../lib/vivado_ipi/axi_bitq/axi_bitq.vhd +set_global_assignment -name QIP_FILE ../ip/oddr/oddr.qip +set_global_assignment -name SOURCE_FILE db/mb_cpld.cmp.rdb +set_global_assignment -name PARTITION_NETLIST_TYPE POST_FIT -section_id "PcieCmi:PcieCmix" +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id "PcieCmi:PcieCmix" +set_global_assignment -name PARTITION_COLOR 52377 -section_id "PcieCmi:PcieCmix" +set_global_assignment -name PARTITION_IMPORT_FILE ../ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix" +set_global_assignment -name PARTITION_LAST_IMPORTED_FILE ip/cmi/PcieCmi.qxp -section_id "PcieCmi:PcieCmix" +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY pciec_5b6b1 -to "PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix" -section_id "PcieCmi:PcieCmix" \ No newline at end of file diff --git a/fpga/usrp3/top/x400/cpld/quartus/ps_cs_analysis.tcl b/fpga/usrp3/top/x400/cpld/quartus/ps_cs_analysis.tcl new file mode 100644 index 000000000..03ff77d2c --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/quartus/ps_cs_analysis.tcl @@ -0,0 +1,32 @@ +# +# Copyright 2021 Ettus Research, a National Instruments Brand +# +# SPDX-License-Identifier: LGPL-3.0-or-later +# +# Module: ps_cs_analysis +# +# Description: +# +# Analyze false path in PS SPI logic to ensure an upper delay boundary. +# + +# get project to a working state +project_open -force "mb_cpld.qpf" +create_timing_netlist +update_timing_netlist + +# Determine data path delay from MB CPLD chip select signal to MB CPLD internal +# SPI slave +set paths [report_path -from [get_registers {ps_spi_cs_n_decoded[0]}] -multi_corner] +set spiSlaveCsPathDelay [lindex $paths 1] + +# clock period at 250 MHz (clock driving the decoding registers) +set maxDelay 4 + +# compare path from above with maximum delay +if ([expr {$maxDelay < $spiSlaveCsPathDelay}]) { + puts "MB CPLD SPI CS line longer than expected." + exit 1 +} + +exit 0 diff --git a/fpga/usrp3/top/x400/cpld/quartus/raw_conversion.cof b/fpga/usrp3/top/x400/cpld/quartus/raw_conversion.cof new file mode 100644 index 000000000..87ecb15d8 --- /dev/null +++ b/fpga/usrp3/top/x400/cpld/quartus/raw_conversion.cof @@ -0,0 +1,39 @@ + + + output_files/mb_cpld_converted.pof + 1 + 1 + 14 + + Page_0 + 1 + + output_files/mb_cpld.sof1 + + + 10 + 0 + 0 + 1 + 1 + + 1 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + + + 1 + 2 + 0 + -1 + -1 + 1 + + \ No newline at end of file diff --git a/fpga/usrp3/top/x400/cpld/raw_conversion.cof b/fpga/usrp3/top/x400/cpld/raw_conversion.cof deleted file mode 100644 index 87ecb15d8..000000000 --- a/fpga/usrp3/top/x400/cpld/raw_conversion.cof +++ /dev/null @@ -1,39 +0,0 @@ - - - output_files/mb_cpld_converted.pof - 1 - 1 - 14 - - Page_0 - 1 - - output_files/mb_cpld.sof1 - - - 10 - 0 - 0 - 1 - 1 - - 1 - - - 0 - 1 - 0 - 0 - 0 - 0 - 0 - - - 1 - 2 - 0 - -1 - -1 - 1 - - \ No newline at end of file diff --git a/fpga/usrp3/top/x400/cpld/reconfig_engine.v b/fpga/usrp3/top/x400/cpld/reconfig_engine.v index a7c94b4a2..fc6a4837e 100644 --- a/fpga/usrp3/top/x400/cpld/reconfig_engine.v +++ b/fpga/usrp3/top/x400/cpld/reconfig_engine.v @@ -73,6 +73,29 @@ module reconfig_engine #( `include "regmap/reconfig_regmap_utils.vh" `include "../../../lib/rfnoc/core/ctrlport.vh" + // Check MAX10 variant target (10M04 or 10M08) + `ifdef VARIANT_10M04 + localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT = FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04; + localparam FLASH_PRIMARY_IMAGE_START_ADDR = FLASH_PRIMARY_IMAGE_START_ADDR_10M04; + localparam FLASH_PRIMARY_IMAGE_END_ADDR = FLASH_PRIMARY_IMAGE_END_ADDR_10M04; + localparam CFM0_WP_OFFSET_MSB = 26; // From Max 10 Flash Memory User Guide. + localparam CFM0_WP_OFFSET_LSB = 24; // From Max 10 Flash Memory User Guide. + `elsif VARIANT_10M08 + localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT = FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M08; + localparam FLASH_PRIMARY_IMAGE_START_ADDR = FLASH_PRIMARY_IMAGE_START_ADDR_10M08; + localparam FLASH_PRIMARY_IMAGE_END_ADDR = FLASH_PRIMARY_IMAGE_END_ADDR_10M08; + localparam CFM0_WP_OFFSET_MSB = 27; // From Max 10 Flash Memory User Guide. + localparam CFM0_WP_OFFSET_LSB = 25; // From Max 10 Flash Memory User Guide. + `else + ERROR_MAX10_variant_must_be_defined(); + localparam FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT = FLASH_PRIMARY_IMAGE_START_ADDR_MEM_INIT_10M04; + localparam FLASH_PRIMARY_IMAGE_START_ADDR = FLASH_PRIMARY_IMAGE_START_ADDR_10M04; + localparam FLASH_PRIMARY_IMAGE_END_ADDR = FLASH_PRIMARY_IMAGE_END_ADDR_10M04; + localparam CFM0_WP_OFFSET_MSB = 26; // From Max 10 Flash Memory User Guide. + localparam CFM0_WP_OFFSET_LSB = 24; // From Max 10 Flash Memory User Guide. + `endif + + //---------------------------------------------------------- // Flash Interface between Registers and State Machine //---------------------------------------------------------- @@ -264,8 +287,7 @@ module reconfig_engine #( localparam CONTROL_REG_ADDR = 1'b1; localparam SECTOR_ERASE_ADDR_MSB = 22; localparam SECTOR_ERASE_ADDR_LSB = 20; - localparam CFM0_WP_OFFSET_MSB = 26; - localparam CFM0_WP_OFFSET_LSB = 24; + // CFM0_WP_OFFSET_MSB and CFM0_WP_OFFSET_LSB are MAX10 variant dependent. localparam ENABLE_WP = MEM_INIT ? 3'b111 : 3'b100; localparam DISABLE_WP = 3'b000; @@ -742,17 +764,26 @@ endmodule // // // -// Those values are the start and end address of the CFM image flash -// sector from Intel's On-Chip Flash IP Generator. Note that the values -// given in the IP generator are byte based where the values of this enum -// are U32 based (divided by 4). +// These values are the start and end address of the CFM image flash +// sector from Intel's On-Chip Flash IP Generator. +// Be aware that three different values exist per each of the two +// supported MAX10 variants: 10M04 and 10M08 +// Note that the values given in the IP generator are byte based where +// the values of this enum are U32 based (divided by 4). // -// -// -// +// +// +// +// // // @@ -948,9 +979,12 @@ endmodule // Defines the sector to be erased. Has to be set latest with the // write access which starts the erase operation by strobing // @.FLASH_ERASE_STB.{br} -// If the flash is configured to support memory initialization (see -// @.FLASH_MEM_INIT_ENABLED flag) the sectors 2 to 4 have to be erased. -// If the flag is not asserted only sector 4 has to be erased. +// With 10M04 variants, if the flash is configured to support memory +// initialization (see @.FLASH_MEM_INIT_ENABLED flag) the sectors 2 +// to 4 have to be erased. If the flag is not asserted only sector 4 +// has to be erased. +// With 10M08 variants, the sectors to be erased are 3 to 5 when +// using memory initialization or only sector 5 otherwise. // // //