From 0df4b801a34697f2058b4a7b95e08d2a0576c9db Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Thu, 10 Oct 2013 10:17:27 -0700 Subject: Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus. --- fpga/usrp3/top/b200/S6CLK2PIN.v | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 fpga/usrp3/top/b200/S6CLK2PIN.v (limited to 'fpga/usrp3/top/b200/S6CLK2PIN.v') diff --git a/fpga/usrp3/top/b200/S6CLK2PIN.v b/fpga/usrp3/top/b200/S6CLK2PIN.v new file mode 100644 index 000000000..a9d6332ef --- /dev/null +++ b/fpga/usrp3/top/b200/S6CLK2PIN.v @@ -0,0 +1,23 @@ +module S6CLK2PIN +( + input I, + output O +); + + ODDR2 #( + .DDR_ALIGNMENT("NONE"), // to "NONE", "C0" or "C1" + .INIT(1'b0), // output to 1'b0 or 1'b1 + .SRTYPE("ASYNC")) // set/reset "SYNC" or "ASYNC" + + ODDR2_S6CLK2PIN + ( + .Q(O), // 1-bit DDR output data + .C0(I), // 1-bit clock input + .C1(~I), // 1-bit clock input + .CE(1'b1), // 1-bit clock enable input + .D0(1'b1), // 1-bit data input (associated with C0) + .D1(1'b0), // 1-bit data input (associated with C1) + .R(1'b0), // 1-bit reset input + .S(1'b0) );// 1-bit set input + +endmodule //S6CLK2PIN -- cgit v1.2.3