From fba23eb42c91ca1bc1108b5ba50c1b567cb9b59d Mon Sep 17 00:00:00 2001 From: Humberto Jimenez Date: Thu, 13 Dec 2018 16:35:50 -0600 Subject: fpga: tools: Add support for RFSoC This commit includes the following changes to the tools: - Change part definition in XCI and BD editors for the RFSoC family - Resolve part name in Vivado IP management utilities with viv_gen_part_id.py --- fpga/usrp3/tools/scripts/viv_ip_xci_editor.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'fpga/usrp3/tools/scripts/viv_ip_xci_editor.py') diff --git a/fpga/usrp3/tools/scripts/viv_ip_xci_editor.py b/fpga/usrp3/tools/scripts/viv_ip_xci_editor.py index b749b76da..8648c8b5e 100644 --- a/fpga/usrp3/tools/scripts/viv_ip_xci_editor.py +++ b/fpga/usrp3/tools/scripts/viv_ip_xci_editor.py @@ -57,7 +57,11 @@ def main(): if args.action == 'read_partid': print(xci_info['DEVICE'] + '/' + xci_info['PACKAGE'] + '/' + xci_info['SPEEDGRADE'] + '/' + xci_info['TEMPERATURE_GRADE'] + '/' + xci_info['SILICON_REVISION']) if args.action == 'read_part': - print(xci_info['DEVICE'] + xci_info['PACKAGE'] + xci_info['SPEEDGRADE']) + # The UltraScale+ RFSoC family ids are expected diferently in Vivado, a '-' must separate each property. + if xci_info['ARCHITECTURE'] == "zynquplusRFSOC": + print(xci_info['DEVICE'] + "-" + xci_info['PACKAGE'] + xci_info['SPEEDGRADE'] + "-" + xci_info['TEMPERATURE_GRADE']) + else: + print(xci_info['DEVICE'] + xci_info['PACKAGE'] + xci_info['SPEEDGRADE']) elif args.action == 'retarget': # Write a new XCI file with modified target info if not os.path.isdir(args.output_dir): -- cgit v1.2.3