From 66267f515802ff3f965fd44e1f0d3097ada7484f Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Wed, 1 Sep 2021 15:27:45 -0500 Subject: fpga: tools: Add UHD_FPGA_DIR definition to synthesis This adds a Verilog definition named `UHD_FPGA_DIR that corresponds to the location of the UHD "fpga" directory. This allows you to include files in your out-of-tree modules relative to the FPGA directory. For example, you could include the library header file rfnoc_chdr_utils.vh using the following: `include `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`" Some simulators may not support `" outside of the context of a `define, in which case you can do the following: `define RFNOC_CHDR_UTILS_PATH \ `"`UHD_FPGA_DIR/usrp3/lib/rfnoc/core/rfnoc_chdr_utils.vh`" `include `RFNOC_CHDR_UTILS_PATH --- fpga/usrp3/tools/make/viv_design_builder.mak | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'fpga/usrp3/tools/make/viv_design_builder.mak') diff --git a/fpga/usrp3/tools/make/viv_design_builder.mak b/fpga/usrp3/tools/make/viv_design_builder.mak index 74f1ef034..3ca44b01b 100644 --- a/fpga/usrp3/tools/make/viv_design_builder.mak +++ b/fpga/usrp3/tools/make/viv_design_builder.mak @@ -25,7 +25,7 @@ BUILD_VIVADO_DESIGN = \ export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ export VIV_MODE=$(VIVADO_MODE); \ export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \ - export VIV_VERILOG_DEFS="$(VERILOG_DEFS)"; \ + export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \ cd $(BUILD_DIR); \ $(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(BUILD_DIR)/../dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou @@ -50,7 +50,7 @@ CHECK_VIVADO_DESIGN = \ export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ export VIV_MODE=$(VIVADO_MODE); \ export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(DESIGN_SRCS)); \ - export VIV_VERILOG_DEFS="$(VERILOG_DEFS)"; \ + export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)../../"; \ cd $(BUILD_DIR); \ $(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(TOOLS_DIR)/scripts/check_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou -- cgit v1.2.3