From e962cc4a5e51e2326eb656ee2a779ea26774687b Mon Sep 17 00:00:00 2001 From: Wade Fife Date: Thu, 2 Jul 2020 13:50:23 -0500 Subject: fpga: rfnoc: Fix testbenches to run under ModelSim This updates the makefiles for the testbenches so they can be run using "make modelsim" without any additional hacks. The "xsim" and "vsim" simulation targets also still work. --- fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile.srcs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile.srcs') diff --git a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile.srcs b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile.srcs index 21ba967f2..b2d823453 100644 --- a/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile.srcs +++ b/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/Makefile.srcs @@ -1,5 +1,5 @@ # -# Copyright 2019 Ettus Research, A National Instruments Company +# Copyright 2019 Ettus Research, a National Instruments Brand # # SPDX-License-Identifier: LGPL-3.0-or-later # -- cgit v1.2.3