From 0df4b801a34697f2058b4a7b95e08d2a0576c9db Mon Sep 17 00:00:00 2001
From: Ben Hilburn <ben.hilburn@ettus.com>
Date: Thu, 10 Oct 2013 10:17:27 -0700
Subject: Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt
 Ettus.

---
 fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v | 38 +++++++++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v

(limited to 'fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v')

diff --git a/fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v b/fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v
new file mode 100644
index 000000000..8d9ccf948
--- /dev/null
+++ b/fpga/usrp3/lib/packet_proc/ip_hdr_checksum_tb.v
@@ -0,0 +1,38 @@
+
+module ip_hdr_checksum_tb();
+   
+   initial $dumpfile("ip_hdr_checksum_tb.vcd");
+   initial $dumpvars(0,ip_hdr_checksum_tb);
+
+   reg clk;
+   
+   wire [159:0] in = {
+		      16'h4500,
+		      16'h0030,
+		      16'h4422,
+		      16'h4000,
+		      16'h8006,
+		      16'h0000,
+		      16'h8c7c,
+		      16'h19ac,
+		      16'hae24,
+		      16'h1e2b
+		      };
+   
+   wire [15:0] 	out;
+   ip_hdr_checksum ip_hdr_checksum
+     (.clk(clk), 
+      .in(in),
+      .out(out));
+
+   initial
+     begin
+	clk <= 0;
+	#100 clk <= 1;
+	#100 clk <= 0;
+	#100 clk <= 1;
+	#100 $display("Computed 0x%x, should be 0x442e", out);
+	#100 $finish;
+     end
+   
+endmodule // ip_hdr_checksum_tb
-- 
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