From bafa9d95453387814ef25e6b6256ba8db2df612f Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Thu, 23 Jan 2020 16:10:22 -0800 Subject: Merge FPGA repository back into UHD repository MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams Co-authored-by: Andrej Rode Co-authored-by: Ashish Chaudhari Co-authored-by: Ben Hilburn Co-authored-by: Ciro Nishiguchi Co-authored-by: Daniel Jepson Co-authored-by: Derek Kozel Co-authored-by: EJ Kreinar Co-authored-by: Humberto Jimenez Co-authored-by: Ian Buckley Co-authored-by: Jörg Hofrichter Co-authored-by: Jon Kiser Co-authored-by: Josh Blum Co-authored-by: Jonathon Pendlum Co-authored-by: Martin Braun Co-authored-by: Matt Ettus Co-authored-by: Michael West Co-authored-by: Moritz Fischer Co-authored-by: Nick Foster Co-authored-by: Nicolas Cuervo Co-authored-by: Paul Butler Co-authored-by: Paul David Co-authored-by: Ryan Marlow Co-authored-by: Sugandha Gupta Co-authored-by: Sylvain Munaut Co-authored-by: Trung Tran Co-authored-by: Vidush Vishwanath Co-authored-by: Wade Fife --- fpga/usrp3/lib/io_port2/create-lvbitx.py | 153 +++++++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) create mode 100644 fpga/usrp3/lib/io_port2/create-lvbitx.py (limited to 'fpga/usrp3/lib/io_port2/create-lvbitx.py') diff --git a/fpga/usrp3/lib/io_port2/create-lvbitx.py b/fpga/usrp3/lib/io_port2/create-lvbitx.py new file mode 100644 index 000000000..ea8231292 --- /dev/null +++ b/fpga/usrp3/lib/io_port2/create-lvbitx.py @@ -0,0 +1,153 @@ +#!/usr/bin/python +""" +Generate lvbitx from template and bitfile +""" + +from __future__ import print_function +from xml.etree import ElementTree +import optparse +import base64 +import os +from hashlib import md5 + +def to_native_str(str_or_bstr): + """ + Returns a native string, regardless of the input string type (binary or + UTF-8), and the Python version (2 or 3). + Note that the native string type is actually not the same in Python 2 and + 3: In the former, it's a binary string, in the latter, it's Unicode. + >>> to_native_str(b'foo') + 'foo' + >>> to_native_str(u'foo') + 'foo' + """ + if isinstance(str_or_bstr, str): + return str_or_bstr + try: + # This will either fail because we're running Python 2 (which doesn't) + # have the encoding argument) or because we're not passing in a bytes- + # like object (e.g., an integer) + return str(str_or_bstr, encoding='ascii') + except TypeError: + return str(str_or_bstr) + +def get_parser(): + """Parse args.""" + parser = optparse.OptionParser() + parser.add_option( + "--device", + type="string", + dest="device_type", + help="Device Type. (Has to match the LVFPGA target plugin)", + default=None + ) + parser.add_option( + "--input-bin", + type="string", + dest="input_bin", + help="Path to bin file that needs to be merged with the LVBITX before exporting", + default=None + ) + parser.add_option( + "--output-bin", + type="string", + dest="output_bin", + help="Create a binary configuration bitstream", + default=None + ) + parser.add_option( + "--output-lvbitx", + type="string", + dest="output_lvbitx_path", + help="Output path for autogenerated LVBITX file", + default=None + ) + parser.add_option( + "--output-src-path", + type="string", + dest="output_src_path", + help="Output path for autogenerated src file", + default=None + ) + return parser + +def main(): + """Go, go, go!""" + parser = get_parser() + options, args = parser.parse_args() + # Args + if len(args) < 1: + print('ERROR: Please specify the input LVBITX file name') + parser.print_help() + exit(1) + + lvbitx_filename = args[0] + input_filename = os.path.abspath(lvbitx_filename) + + if not os.path.isfile(input_filename): + print("ERROR: LVBITX File `{}' could not be accessed or is not a file." + .format(input_filename)) + parser.print_help() + exit(1) + + if options.input_bin is not None and \ + not os.path.isfile(os.path.abspath(options.input_bin)): + print("ERROR: FPGA Bin File `{}' could not be accessed or is not a file." + .format(options.input_bin)) + parser.print_help() + exit(1) + + if options.output_lvbitx_path is not None and \ + input_filename == options.output_lvbitx_path: + print('ERROR: Input and output LVBITX files were the same. ' + 'Choose a difference input or output file.') + parser.print_help() + exit(1) + + # Get XML Tree Node + tree = ElementTree.parse(input_filename) + root = tree.getroot() + + # Update device type + if options.device_type is not None: + root.find('Project').find('TargetClass').text += '; ' + options.device_type + + # Merge bitstream into LVBITX + if options.input_bin is not None: + with open(os.path.abspath(options.input_bin), 'rb') as bin_file: + bitstream = bin_file.read() + bitstream_md5 = md5(bitstream).hexdigest() + bitstream_b64 = base64.b64encode(bitstream) + bitstream_b64_lb = b'\n'.join([ + bitstream_b64[i:i+76] + for i in range(0, len(bitstream_b64), 76) + ]) + b'\n' + root.find('Bitstream').text = to_native_str(bitstream_b64_lb) + root.find('BitstreamMD5').text = bitstream_md5 + + # Write BIN file + bitstream = base64.b64decode(root.find('Bitstream').text) + if options.output_lvbitx_path is not None \ + and md5(bitstream).hexdigest() != root.find('BitstreamMD5').text: + print('ERROR: The MD5 sum for the output LVBITX was incorrect. ' + 'Make sure that the bitstream in the input LVBITX or BIN file is valid.') + exit(1) + + if options.output_bin is not None: + fpga_bin_file = open(options.output_bin, 'wb') + fpga_bin_file.write(bitstream) + fpga_bin_file.close() + + # Save LVBITX + if options.output_lvbitx_path is not None: + with open(options.output_lvbitx_path, 'wb') as lvbitx_file: + tree.write( + lvbitx_file, + encoding="utf-8", + xml_declaration=True, + default_namespace=None, + method="xml" + ) + +if __name__ == "__main__": + main() -- cgit v1.2.3