From 0df4b801a34697f2058b4a7b95e08d2a0576c9db Mon Sep 17 00:00:00 2001
From: Ben Hilburn <ben.hilburn@ettus.com>
Date: Thu, 10 Oct 2013 10:17:27 -0700
Subject: Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt
 Ettus.

---
 fpga/usrp3/lib/dsp/sign_extend.v | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 fpga/usrp3/lib/dsp/sign_extend.v

(limited to 'fpga/usrp3/lib/dsp/sign_extend.v')

diff --git a/fpga/usrp3/lib/dsp/sign_extend.v b/fpga/usrp3/lib/dsp/sign_extend.v
new file mode 100644
index 000000000..7c85920aa
--- /dev/null
+++ b/fpga/usrp3/lib/dsp/sign_extend.v
@@ -0,0 +1,23 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2003 Matt Ettus
+//
+
+//
+
+
+// Sign extension "macro"
+// bits_out should be greater than bits_in
+
+module sign_extend (in,out);
+	parameter bits_in=0;  // FIXME Quartus insists on a default
+	parameter bits_out=0;
+	
+	input [bits_in-1:0] in;
+	output [bits_out-1:0] out;
+	
+	assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
+	
+endmodule
-- 
cgit v1.2.3