From fd3e84941de463fa1a7ebab0a69515b4bf2614cd Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Tue, 7 Oct 2014 11:25:20 +0200 Subject: Removed copy of FPGA source files. --- fpga/usrp3/lib/dsp/add2_and_round_reg.v | 21 --------------------- 1 file changed, 21 deletions(-) delete mode 100644 fpga/usrp3/lib/dsp/add2_and_round_reg.v (limited to 'fpga/usrp3/lib/dsp/add2_and_round_reg.v') diff --git a/fpga/usrp3/lib/dsp/add2_and_round_reg.v b/fpga/usrp3/lib/dsp/add2_and_round_reg.v deleted file mode 100644 index cb20a3c1b..000000000 --- a/fpga/usrp3/lib/dsp/add2_and_round_reg.v +++ /dev/null @@ -1,21 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// - - - -module add2_and_round_reg - #(parameter WIDTH=16) - (input clk, - input [WIDTH-1:0] in1, - input [WIDTH-1:0] in2, - output reg [WIDTH-1:0] sum); - - wire [WIDTH-1:0] sum_int; - - add2_and_round #(.WIDTH(WIDTH)) add2_n_rnd (.in1(in1),.in2(in2),.sum(sum_int)); - - always @(posedge clk) - sum <= sum_int; - -endmodule // add2_and_round_reg -- cgit v1.2.3