From 0df4b801a34697f2058b4a7b95e08d2a0576c9db Mon Sep 17 00:00:00 2001 From: Ben Hilburn Date: Thu, 10 Oct 2013 10:17:27 -0700 Subject: Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt Ettus. --- fpga/usrp3/lib/dsp/add2_and_round_reg.v | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 fpga/usrp3/lib/dsp/add2_and_round_reg.v (limited to 'fpga/usrp3/lib/dsp/add2_and_round_reg.v') diff --git a/fpga/usrp3/lib/dsp/add2_and_round_reg.v b/fpga/usrp3/lib/dsp/add2_and_round_reg.v new file mode 100644 index 000000000..cb20a3c1b --- /dev/null +++ b/fpga/usrp3/lib/dsp/add2_and_round_reg.v @@ -0,0 +1,21 @@ +// +// Copyright 2011 Ettus Research LLC +// + + + +module add2_and_round_reg + #(parameter WIDTH=16) + (input clk, + input [WIDTH-1:0] in1, + input [WIDTH-1:0] in2, + output reg [WIDTH-1:0] sum); + + wire [WIDTH-1:0] sum_int; + + add2_and_round #(.WIDTH(WIDTH)) add2_n_rnd (.in1(in1),.in2(in2),.sum(sum_int)); + + always @(posedge clk) + sum <= sum_int; + +endmodule // add2_and_round_reg -- cgit v1.2.3