From 0df4b801a34697f2058b4a7b95e08d2a0576c9db Mon Sep 17 00:00:00 2001
From: Ben Hilburn <ben.hilburn@ettus.com>
Date: Thu, 10 Oct 2013 10:17:27 -0700
Subject: Squashed B200 FPGA Source. Code from Josh Blum, Ian Buckley, and Matt
 Ettus.

---
 fpga/usrp3/lib/control/dram_2port.v | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 fpga/usrp3/lib/control/dram_2port.v

(limited to 'fpga/usrp3/lib/control/dram_2port.v')

diff --git a/fpga/usrp3/lib/control/dram_2port.v b/fpga/usrp3/lib/control/dram_2port.v
new file mode 100644
index 000000000..186af44e7
--- /dev/null
+++ b/fpga/usrp3/lib/control/dram_2port.v
@@ -0,0 +1,27 @@
+////////////////////////////////////////////////////////////////////////
+// Copyright Ettus Research LLC
+////////////////////////////////////////////////////////////////////////
+
+module dram_2port
+  #(parameter DWIDTH=32,
+    parameter AWIDTH=9)
+    (input clk,
+     input write,
+     input [AWIDTH-1:0] raddr,
+     input [AWIDTH-1:0] waddr,
+     input [DWIDTH-1:0] wdata,
+     output [DWIDTH-1:0] rdata);
+
+    reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0];
+   integer 	    i;
+   initial
+     for(i=0;i<(1<<AWIDTH);i=i+1)
+       ram[i] <= {DWIDTH{1'b0}};
+
+    assign rdata = ram[raddr];
+
+    always @(posedge clk) begin
+        if (write) ram[waddr] <= wdata;
+    end
+
+endmodule //dram_2port
-- 
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