From bafa9d95453387814ef25e6b6256ba8db2df612f Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Thu, 23 Jan 2020 16:10:22 -0800 Subject: Merge FPGA repository back into UHD repository MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams Co-authored-by: Andrej Rode Co-authored-by: Ashish Chaudhari Co-authored-by: Ben Hilburn Co-authored-by: Ciro Nishiguchi Co-authored-by: Daniel Jepson Co-authored-by: Derek Kozel Co-authored-by: EJ Kreinar Co-authored-by: Humberto Jimenez Co-authored-by: Ian Buckley Co-authored-by: Jörg Hofrichter Co-authored-by: Jon Kiser Co-authored-by: Josh Blum Co-authored-by: Jonathon Pendlum Co-authored-by: Martin Braun Co-authored-by: Matt Ettus Co-authored-by: Michael West Co-authored-by: Moritz Fischer Co-authored-by: Nick Foster Co-authored-by: Nicolas Cuervo Co-authored-by: Paul Butler Co-authored-by: Paul David Co-authored-by: Ryan Marlow Co-authored-by: Sugandha Gupta Co-authored-by: Sylvain Munaut Co-authored-by: Trung Tran Co-authored-by: Vidush Vishwanath Co-authored-by: Wade Fife --- fpga/usrp3/lib/control/ad5662_auto_spi.v | 99 ++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 fpga/usrp3/lib/control/ad5662_auto_spi.v (limited to 'fpga/usrp3/lib/control/ad5662_auto_spi.v') diff --git a/fpga/usrp3/lib/control/ad5662_auto_spi.v b/fpga/usrp3/lib/control/ad5662_auto_spi.v new file mode 100644 index 000000000..d9f2e53be --- /dev/null +++ b/fpga/usrp3/lib/control/ad5662_auto_spi.v @@ -0,0 +1,99 @@ +// +// Copyright 2015 Ettus Research +// Copyright 2018 Ettus Research, a National Instruments Company +// +// SPDX-License-Identifier: LGPL-3.0-or-later +// +// The AD5662 DAC serial interface uses 24-bit transfers to encode 16-bits +// of actual data, two bits for power-down mode, and six pad bits. This +// module stores a copy of the last-programmed value, and will generate a +// serial stream if ever the input word (dat) changes. It will ignore +// changes to (dat) while it is busy with a serial update. +// +module ad5662_auto_spi +( + input clk, + input [15:0] dat, + output reg sclk, + output reg mosi, + output reg sync_n +); + // initialize ldat to 0, thus forcing + // a reload on init. + reg [15:0] ldat = 16'd0; + wire upd = (dat != ldat); // new data present, need to update hw + + reg [23:0] shft=24'b0; + wire [23:0] nxt_shft; + + // clock cycle counter to throttle generated spi cycles + // allowing one spi clock cycle every 16 cycles of clk, with clk at 200 MHz + // gives a spi clock rate of 12 MHz. This can be made more sophisticated + // or parameterized, if more flexibility in clk is needed, of course. + reg [3:0] ccnt=4'b0; + wire [3:0] nxt_ccnt = ccnt + 1'b1; + wire half = ccnt==4'b1000; + wire full = ccnt==4'b1111; + reg sena, hena; + wire cena; + always @(posedge clk) if (cena) ccnt <= nxt_ccnt; + always @(posedge clk) sena <= full; // state updates and rising sclk + always @(posedge clk) hena <= half; // for falling sclk + + // transfer state counter + reg [4:0] scnt = 5'b0; + reg [4:0] nxt_scnt; + always @(posedge clk) begin + if (sena) begin + scnt <= nxt_scnt; + shft <= nxt_shft; + mosi <= shft[23]; + end + end + + + // 32 possible states - more than enough to shift-out 24 bits and manage + // the sync_n line + + // particular scnt values of interest + localparam READY=5'b00000; // waiting for new data + localparam DCAPT=5'b00001; // new data transfers into ldat + localparam SYNCL=5'b00010; // assert sync_n low + localparam SYNCH=5'b11011; // return sync_n high + + assign cena = upd | scnt != READY; + + always @(scnt or upd) + begin + case (scnt) + READY: + nxt_scnt = upd ? DCAPT : READY; + SYNCH: + nxt_scnt = READY; + default: + nxt_scnt = scnt + 1'b1; + endcase + end + + // note: defining the power-down mode bits to 00 for "normal operation" + assign nxt_shft = (scnt == SYNCL) ? { 8'b000000_00, ldat } : { shft[22:0], 1'b0 }; + + // Update ldat when dat has changed, but only if READY. + // Changes to dat arriving faster than can be kept up with here are ignored + // until the cycle-in-progress is completed. + wire ldat_ena = sena & (scnt == DCAPT); + always @(posedge clk) begin + if (ldat_ena) ldat <= dat; + end + + // keep the sync_n line low when idle to minimize power consumption + // it gets brought high just before beginning each transaction + wire nxt_sync_n = (scnt==SYNCL) | (scnt==SYNCH); + always @(posedge clk) if (sena) sync_n <= nxt_sync_n; + + reg sclk_go; + always @(posedge clk) sclk_go <= (scnt > SYNCL); + wire nxt_sclk = ~sclk_go ? 1'b1 : ~sclk; + always @(posedge clk) if (sena | hena) sclk <= nxt_sclk; + +endmodule -- cgit v1.2.3