From fd3e84941de463fa1a7ebab0a69515b4bf2614cd Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Tue, 7 Oct 2014 11:25:20 +0200 Subject: Removed copy of FPGA source files. --- fpga/usrp3/lib/axi/axi_chdr_header_trigger.v | 40 ---------------------------- 1 file changed, 40 deletions(-) delete mode 100644 fpga/usrp3/lib/axi/axi_chdr_header_trigger.v (limited to 'fpga/usrp3/lib/axi/axi_chdr_header_trigger.v') diff --git a/fpga/usrp3/lib/axi/axi_chdr_header_trigger.v b/fpga/usrp3/lib/axi/axi_chdr_header_trigger.v deleted file mode 100644 index e8dee3675..000000000 --- a/fpga/usrp3/lib/axi/axi_chdr_header_trigger.v +++ /dev/null @@ -1,40 +0,0 @@ - -// Copyright 2014 Ettus Research LLC - - -module axi_chdr_header_trigger - #( - parameter WIDTH=64, - parameter SID=0 - ) - (input clk, input reset, input clear, - input [WIDTH-1:0] i_tdata, input i_tlast, input i_tvalid, input i_tready, - output trigger - ); - - - reg state; - localparam IDLE = 0; - localparam RUN = 1; - - - always @(posedge clk) - if(reset | clear) - state <= IDLE; - else - case (state) - IDLE : - if(i_tvalid && i_tready) - state <= RUN; - - RUN : - if(i_tready && i_tvalid && i_tlast) - state <= IDLE; - - default : - state <= IDLE; - endcase // case (state) - - assign trigger = i_tvalid && i_tready && (state == IDLE) && (i_tdata[15:0] != SID); - -endmodule // axi_chdr_header_trigger -- cgit v1.2.3