From fd3e84941de463fa1a7ebab0a69515b4bf2614cd Mon Sep 17 00:00:00 2001
From: Martin Braun <martin.braun@ettus.com>
Date: Tue, 7 Oct 2014 11:25:20 +0200
Subject: Removed copy of FPGA source files.

---
 fpga/usrp2/extramfifo/icon.xco | 47 ------------------------------------------
 1 file changed, 47 deletions(-)
 delete mode 100644 fpga/usrp2/extramfifo/icon.xco

(limited to 'fpga/usrp2/extramfifo/icon.xco')

diff --git a/fpga/usrp2/extramfifo/icon.xco b/fpga/usrp2/extramfifo/icon.xco
deleted file mode 100644
index fda273149..000000000
--- a/fpga/usrp2/extramfifo/icon.xco
+++ /dev/null
@@ -1,47 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 12.1
-# Date: Wed Jul 21 03:31:19 2010
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = Verilog
-SET device = xc3s2000
-SET devicefamily = spartan3
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = fg456
-SET removerpms = false
-SET simulationfiles = Structural
-SET speedgrade = -5
-SET verilogsim = true
-SET vhdlsim = false
-# END Project Options
-# BEGIN Select
-SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.04.a
-# END Select
-# BEGIN Parameters
-CSET component_name=icon
-CSET enable_jtag_bufg=true
-CSET number_control_ports=1
-CSET use_ext_bscan=false
-CSET use_softbscan=false
-CSET use_unused_bscan=false
-CSET user_scan_chain=USER1
-# END Parameters
-GENERATE
-# CRC: 799ba5a1
-- 
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