From fd3e84941de463fa1a7ebab0a69515b4bf2614cd Mon Sep 17 00:00:00 2001 From: Martin Braun Date: Tue, 7 Oct 2014 11:25:20 +0200 Subject: Removed copy of FPGA source files. --- fpga/usrp2/control_lib/reset_sync.v | 33 --------------------------------- 1 file changed, 33 deletions(-) delete mode 100644 fpga/usrp2/control_lib/reset_sync.v (limited to 'fpga/usrp2/control_lib/reset_sync.v') diff --git a/fpga/usrp2/control_lib/reset_sync.v b/fpga/usrp2/control_lib/reset_sync.v deleted file mode 100644 index 304aba106..000000000 --- a/fpga/usrp2/control_lib/reset_sync.v +++ /dev/null @@ -1,33 +0,0 @@ -// -// Copyright 2011 Ettus Research LLC -// -// This program is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published by -// the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - - - -module reset_sync - (input clk, - input reset_in, - output reg reset_out); - - reg reset_int; - - always @(posedge clk or posedge reset_in) - if(reset_in) - {reset_out,reset_int} <= 2'b11; - else - {reset_out,reset_int} <= {reset_int,1'b0}; - -endmodule // reset_sync -- cgit v1.2.3