From 830455fae53e9e63146798ba075460cfa2e6ae3a Mon Sep 17 00:00:00 2001
From: Wade Fife <wade.fife@ettus.com>
Date: Tue, 8 Sep 2020 20:04:56 -0500
Subject: fpga: docs: Update user manual for UHD 4.0

---
 fpga/docs/usrp3/vivado_env_utils.md | 43 ++++++++++++++++++++++++++-----------
 1 file changed, 30 insertions(+), 13 deletions(-)

(limited to 'fpga/docs/usrp3/vivado_env_utils.md')

diff --git a/fpga/docs/usrp3/vivado_env_utils.md b/fpga/docs/usrp3/vivado_env_utils.md
index ad5c6266e..601b9b5a5 100644
--- a/fpga/docs/usrp3/vivado_env_utils.md
+++ b/fpga/docs/usrp3/vivado_env_utils.md
@@ -2,22 +2,23 @@
 
 ## Environment Setup
 
-- Navigate to `usrp3/top/{project}` where project is:
-  + x300: For USRP X300 and USRP X310
-  + e3xx: For USRP E310
-  + e320: For USRP E320
-  + n3xx: For USRP N300/N310/N320
+- Navigate to `<repo>/fpga/usrp3/top/{project}` where {project} is:
+  + `x300:` For USRP X300/X310
+  + `e31x:` For USRP E310
+  + `e320:` For USRP E320
+  + `n3xx:` For USRP N300/N310/N320
 
 - To setup up the Ettus Research Xilinx build environment run
   + `source setupenv.sh` (If Vivado is installed in the default path /opt/Xilinx/Vivado) _OR_
   + `source setupenv.sh --vivado-path=<VIVADO_PATH>` (where VIVADO_PATH is a non-default installation path)
 
-- This should not only enable building USRP FPGAs but also make the following utlities available
+- This should not only enable building USRP FPGAs but also make available the
+  utilities described in the following sections.
 
 ## ModelSim Specific
 
-The setupenv.sh script will search the system for ModelSim installations and setup everything to run it natively and
-within Vivado. The currently support versions of ModelSim are PE, DE, SE, DE-64, SE-64.
+The `setupenv.sh` script will search the system for ModelSim installations and setup everything to run it natively and
+within Vivado. The currently supported versions of ModelSim are PE, DE, SE, DE-64, SE-64.
 
 The following functions are also available in the environment:
 
@@ -27,9 +28,9 @@ The following functions are also available in the environment:
 
 ### Create Vivado IP
 
-    viv_create_new_ip: Create a new Vivado IP instance and a Makefile for it
+    viv_create_ip: Create a new Vivado IP instance and a Makefile for it
 
-    Usage: viv_create_new_ip <IP Name> <IP Location> <IP VLNV> <Product>
+    Usage: viv_create_ip <IP Name> <IP Location> <IP VLNV> <Product>
     - <IP Name>: Name of the IP instance
     - <IP Location>: Base location for IP
     - <IP VLNV>: The vendor, library, name, and version (VLNV) string for the IP as defined by Xilinx
@@ -40,7 +41,23 @@ The following functions are also available in the environment:
     viv_modify_ip: Modify an existing Vivado IP instance
 
     Usage: viv_modify_ip <IP XCI Path>
-    - <IP XCI Path>: Path to the IP XCI file.
+    - <IP XCI Path>: Path to the IP XCI file
+
+### Modify existing Vivado Block Design (BD)
+
+    viv_modify_bd: Modify an existing Vivado BD instance
+
+    Usage: viv_modify_bd <BD File Path> <Product>
+    - <BD File Path>: Path to the BD file.
+    - <Product>: Product to generate IP for
+
+### Modify existing Vivado Tcl-based Block Design
+
+    viv_modify_tcl_bd: Modify an existing Vivado BD instance
+
+    Usage: viv_modify_tcl_bd <Tcl File Path> <Product>
+    - <Tcl File Path>: Path to the Tcl file for the block design.
+    - <Product>: Product to generate IP for
 
 ### List supported Vivado IP
 
@@ -62,7 +79,7 @@ The following functions are also available in the environment:
 
     viv_hw_console: Launch the Tcl hardware console
 
-    Usage: viv_upgrade_ip
+    Usage: viv_hw_console
 
 ### List connected JTAG devices
 
@@ -81,7 +98,7 @@ The following functions are also available in the environment:
 
 ### Probe Xilinx bitfile
 
-    probe_bitfile: Probe a Xilinx bit file and report header information
+    probe_bitfile: Probe a Xilinx bitfile and report header information
 
     Usage: probe_bitfile <Bitfile Path>
     - <Bitfile Path>: Path to a .bit FPGA configuration file
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