From 672a77767faf0070e94de0c8acd74328a301cae5 Mon Sep 17 00:00:00 2001
From: Josh Blum <josh@joshknows.com>
Date: Tue, 6 Mar 2012 18:51:31 -0800
Subject: fifo ctrl: ~usrp2_fifo_ctrl acks, usrp2 DCM workaround, bootloader no
 blinkie

---
 firmware/zpu/lib/clocks.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'firmware/zpu/lib/clocks.c')

diff --git a/firmware/zpu/lib/clocks.c b/firmware/zpu/lib/clocks.c
index c1e8ce827..bc1954e13 100644
--- a/firmware/zpu/lib/clocks.c
+++ b/firmware/zpu/lib/clocks.c
@@ -43,7 +43,10 @@ clocks_init(void)
   //enable the 100MHz clock output to the FPGA for 50MHz CPU clock
   clocks_enable_fpga_clk(true, 1);
 
-  spi_wait();
+  //! Cannot SPI wait since SPI is on DSP clock
+  //! because DSP clock goes away until DCM reset.
+  //! However, spi is quick, the cpu is slow, its already ready...
+  //spi_wait();
 
   //wait for the clock to stabilize
   while(!clocks_lock_detect());
-- 
cgit v1.2.3