From 61f2f0214c5999ea42a368a4fc99f03d8eb28d1e Mon Sep 17 00:00:00 2001
From: jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>
Date: Mon, 8 Sep 2008 01:00:12 +0000
Subject: Merged r9433:9527 from features/gr-usrp2 into trunk.  Adds usrp2 and
 gr-usrp2 top-level components.  Trunk passes distcheck with mb-gcc installed,
 but currently not without them.  The key issue is that when mb-gcc is not
 installed, the build system skips over the usrp2/firmware directory, and the
 firmware include files don't get put into the dist tarball.  But we can't do
 the usual DIST_SUBDIRS method as the firmware is a subpackage.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
---
 eth/bench/verilog/files.lst | 42 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 eth/bench/verilog/files.lst

(limited to 'eth/bench/verilog/files.lst')

diff --git a/eth/bench/verilog/files.lst b/eth/bench/verilog/files.lst
new file mode 100644
index 000000000..6175a4d43
--- /dev/null
+++ b/eth/bench/verilog/files.lst
@@ -0,0 +1,42 @@
+../../rtl/verilog/MAC_rx/Broadcast_filter.v
+../../rtl/verilog/MAC_rx/CRC_chk.v
+../../rtl/verilog/MAC_rx/MAC_rx_add_chk.v
+../../rtl/verilog/MAC_rx/MAC_rx_ctrl.v
+../../rtl/verilog/MAC_rx/MAC_rx_FF.v
+
+../../rtl/verilog/MAC_tx/CRC_gen.v
+../../rtl/verilog/MAC_tx/flow_ctrl.v
+../../rtl/verilog/MAC_tx/MAC_tx_addr_add.v
+../../rtl/verilog/MAC_tx/MAC_tx_ctrl.v
+../../rtl/verilog/MAC_tx/MAC_tx_FF.v
+../../rtl/verilog/MAC_tx/Ramdon_gen.v
+
+../../rtl/verilog/miim/eth_clockgen.v
+../../rtl/verilog/miim/eth_outputcontrol.v
+../../rtl/verilog/miim/eth_shiftreg.v
+
+../../rtl/verilog/RMON/RMON_addr_gen.v
+../../rtl/verilog/RMON/RMON_ctrl.v
+../../rtl/verilog/RMON/RMON_dpram.v
+
+../../rtl/verilog/TECH/duram.v
+../../rtl/verilog/TECH/eth_clk_div2.v
+../../rtl/verilog/TECH/eth_clk_switch.v
+
+../../rtl/verilog/TECH/xilinx/BUFGMUX.v
+../../rtl/verilog/TECH/xilinx/RAMB16_S36_S36.v
+
+../../rtl/verilog/Clk_ctrl.v
+../../rtl/verilog/eth_miim.v
+../../rtl/verilog/MAC_rx.v
+../../rtl/verilog/MAC_top.v
+../../rtl/verilog/MAC_tx.v
+../../rtl/verilog/Phy_int.v
+../../rtl/verilog/Reg_int.v
+../../rtl/verilog/RMON.v
+
+../../bench/verilog/Phy_sim.v
+../../bench/verilog/User_int_sim.v
+../../bench/verilog/host_sim.v
+../../bench/verilog/xlnx_glbl.v
+../../bench/verilog/tb_top.v
-- 
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