From 91636cbac2b3edfba45321f1050d0b90b34ab696 Mon Sep 17 00:00:00 2001 From: Johnathan Corgan Date: Mon, 31 Aug 2009 12:08:30 -0700 Subject: Merged SVN matt/new_eth r10782:11633 into new_eth * svn diff http://gnuradio.org/svn/branches/developers/matt/new_eth -r10782:11633 * Patch applied with no conflicts or fuzz. --- control_lib/buffer_pool.v | 323 ---------------------------------------------- 1 file changed, 323 deletions(-) (limited to 'control_lib/buffer_pool.v') diff --git a/control_lib/buffer_pool.v b/control_lib/buffer_pool.v index 969296230..e69de29bb 100644 --- a/control_lib/buffer_pool.v +++ b/control_lib/buffer_pool.v @@ -1,323 +0,0 @@ - -// Buffer pool. Contains 8 buffers, each 2K (512 by 32). Each buffer -// is a dual-ported RAM. Port A on each of them is indirectly connected -// to the wishbone bus by a bridge. Port B may be connected any one of the -// 8 (4 rd, 4 wr) FIFO-like streaming interaces, or disconnected. The wishbone bus -// provides access to all 8 buffers, and also controls the connections -// between the ports and the buffers, allocating them as needed. - -// wb_adr is 16 bits -- -// bits 13:11 select which buffer -// bits 10:2 select line in buffer -// bits 1:0 are unused (32-bit access only) - -module buffer_pool - (input wb_clk_i, - input wb_rst_i, - input wb_we_i, - input wb_stb_i, - input [15:0] wb_adr_i, - input [31:0] wb_dat_i, - output [31:0] wb_dat_o, - output reg wb_ack_o, - output wb_err_o, - output wb_rty_o, - - input stream_clk, - input stream_rst, - - input set_stb, input [7:0] set_addr, input [31:0] set_data, - output [31:0] status, - output sys_int_o, - - output [31:0] s0, output [31:0] s1, output [31:0] s2, output [31:0] s3, - output [31:0] s4, output [31:0] s5, output [31:0] s6, output [31:0] s7, - - // Write Interfaces - input [31:0] wr0_dat_i, input wr0_write_i, input wr0_done_i, input wr0_error_i, output wr0_ready_o, output wr0_full_o, - input [31:0] wr1_dat_i, input wr1_write_i, input wr1_done_i, input wr1_error_i, output wr1_ready_o, output wr1_full_o, - input [31:0] wr2_dat_i, input wr2_write_i, input wr2_done_i, input wr2_error_i, output wr2_ready_o, output wr2_full_o, - input [31:0] wr3_dat_i, input wr3_write_i, input wr3_done_i, input wr3_error_i, output wr3_ready_o, output wr3_full_o, - - // Read Interfaces - output [31:0] rd0_dat_o, input rd0_read_i, input rd0_done_i, input rd0_error_i, output rd0_sop_o, output rd0_eop_o, - output [31:0] rd1_dat_o, input rd1_read_i, input rd1_done_i, input rd1_error_i, output rd1_sop_o, output rd1_eop_o, - output [31:0] rd2_dat_o, input rd2_read_i, input rd2_done_i, input rd2_error_i, output rd2_sop_o, output rd2_eop_o, - output [31:0] rd3_dat_o, input rd3_read_i, input rd3_done_i, input rd3_error_i, output rd3_sop_o, output rd3_eop_o - ); - - wire [7:0] sel_a; - - wire [2:0] which_buf = wb_adr_i[13:11]; // address 15:14 selects the buffer pool - wire [8:0] buf_addra = wb_adr_i[10:2]; // ignore address 1:0, 32-bit access only - - decoder_3_8 dec(.sel(which_buf),.res(sel_a)); - - genvar i; - - wire go; - - reg [2:0] port[0:7]; - reg [3:0] read_src[0:3]; - reg [3:0] write_src[0:3]; - - wire [7:0] done; - wire [7:0] error; - wire [7:0] idle; - - wire [31:0] buf_doa[0:7]; - - wire [7:0] buf_enb; - wire [7:0] buf_web; - wire [8:0] buf_addrb[0:7]; - wire [31:0] buf_dib[0:7]; - wire [31:0] buf_dob[0:7]; - - wire [31:0] wr_dat_i[0:7]; - wire [7:0] wr_write_i; - wire [7:0] wr_done_i; - wire [7:0] wr_error_i; - wire [7:0] wr_ready_o; - wire [7:0] wr_full_o; - - wire [31:0] rd_dat_o[0:7]; - wire [7:0] rd_read_i; - wire [7:0] rd_done_i; - wire [7:0] rd_error_i; - wire [7:0] rd_sop_o; - wire [7:0] rd_eop_o; - - assign status = {8'd0,idle[7:0],error[7:0],done[7:0]}; - - assign s0 = {23'd0,buf_addrb[0]}; - assign s1 = {23'd0,buf_addrb[1]}; - assign s2 = {23'd0,buf_addrb[2]}; - assign s3 = {23'd0,buf_addrb[3]}; - assign s4 = {23'd0,buf_addrb[4]}; - assign s5 = {23'd0,buf_addrb[5]}; - assign s6 = {23'd0,buf_addrb[6]}; - assign s7 = {23'd0,buf_addrb[7]}; - - wire [31:0] fifo_ctrl; - setting_reg #(.my_addr(64)) - sreg(.clk(stream_clk),.rst(stream_rst),.strobe(set_stb),.addr(set_addr),.in(set_data), - .out(fifo_ctrl),.changed(go)); - - integer k; - always @(posedge stream_clk) - if(stream_rst) - for(k=0;k<8;k=k+1) - port[k] <= 4; // disabled - else - for(k=0;k<8;k=k+1) - if(go & (fifo_ctrl[31:28]==k)) - port[k] <= fifo_ctrl[27:25]; - - always @(posedge stream_clk) - if(stream_rst) - for(k=0;k<4;k=k+1) - read_src[k] <= 8; // disabled - else - for(k=0;k<4;k=k+1) - if(go & fifo_ctrl[22] & (fifo_ctrl[27:25]==k)) - read_src[k] <= fifo_ctrl[31:28]; - - always @(posedge stream_clk) - if(stream_rst) - for(k=0;k<4;k=k+1) - write_src[k] <= 8; // disabled - else - for(k=0;k<4;k=k+1) - if(go & fifo_ctrl[23] & (fifo_ctrl[27:25]==k)) - write_src[k] <= fifo_ctrl[31:28]; - - generate - for(i=0;i<8;i=i+1) - begin : gen_buffer - RAMB16_S36_S36 dpram - (.DOA(buf_doa[i]),.ADDRA(buf_addra),.CLKA(wb_clk_i),.DIA(wb_dat_i),.DIPA(4'h0), - .ENA(wb_stb_i & sel_a[i]),.SSRA(0),.WEA(wb_we_i), - .DOB(buf_dob[i]),.ADDRB(buf_addrb[i]),.CLKB(stream_clk),.DIB(buf_dib[i]),.DIPB(4'h0), - .ENB(buf_enb[i]),.SSRB(0),.WEB(buf_web[i]) ); - - /* ram_2port #(.DWIDTH(32),.AWIDTH(9)) buffer - (.clka(wb_clk_i),.ena(wb_stb_i & sel_a[i]),.wea(wb_we_i), - .addra(buf_addra),.dia(wb_dat_i),.doa(buf_doa[i]), - .clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]), - .addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i])); */ - - buffer_int #(.BUFF_NUM(i)) fifo_int - (.clk(stream_clk),.rst(stream_rst), - .ctrl_word(fifo_ctrl),.go(go & (fifo_ctrl[31:28]==i)), - .done(done[i]),.error(error[i]),.idle(idle[i]), - .en_o(buf_enb[i]), - .we_o(buf_web[i]), - .addr_o(buf_addrb[i]), - .dat_to_buf(buf_dib[i]), - .dat_from_buf(buf_dob[i]), - .wr_dat_i(wr_dat_i[i]), - .wr_write_i(wr_write_i[i]), - .wr_done_i(wr_done_i[i]), - .wr_error_i(wr_error_i[i]), - .wr_ready_o(wr_ready_o[i]), - .wr_full_o(wr_full_o[i]), - .rd_dat_o(rd_dat_o[i]), - .rd_read_i(rd_read_i[i]), - .rd_done_i(rd_done_i[i]), - .rd_error_i(rd_error_i[i]), - .rd_sop_o(rd_sop_o[i]), - .rd_eop_o(rd_eop_o[i]) - ); - - // FIXME -- if it is a problem, maybe we don't need enables on these muxes - mux4 #(.WIDTH(32)) - mux4_dat_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_dat_i),.i1(wr1_dat_i), - .i2(wr2_dat_i),.i3(wr3_dat_i),.o(wr_dat_i[i])); - mux4 #(.WIDTH(1)) - mux4_write_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_write_i),.i1(wr1_write_i), - .i2(wr2_write_i),.i3(wr3_write_i),.o(wr_write_i[i])); - mux4 #(.WIDTH(1)) - mux4_wrdone_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_done_i),.i1(wr1_done_i), - .i2(wr2_done_i),.i3(wr3_done_i),.o(wr_done_i[i])); - mux4 #(.WIDTH(1)) - mux4_wrerror_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_error_i),.i1(wr1_error_i), - .i2(wr2_error_i),.i3(wr3_error_i),.o(wr_error_i[i])); - mux4 #(.WIDTH(1)) - mux4_read_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(rd0_read_i),.i1(rd1_read_i), - .i2(rd2_read_i),.i3(rd3_read_i),.o(rd_read_i[i])); - mux4 #(.WIDTH(1)) - mux4_rddone_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(rd0_done_i),.i1(rd1_done_i), - .i2(rd2_done_i),.i3(rd3_done_i),.o(rd_done_i[i])); - mux4 #(.WIDTH(1)) - mux4_rderror_i (.en(~port[i][2]),.sel(port[i][1:0]),.i0(rd0_error_i),.i1(rd1_error_i), - .i2(rd2_error_i),.i3(rd3_error_i),.o(rd_error_i[i])); - end // block: gen_buffer - endgenerate - - //---------------------------------------------------------------------- - // Wishbone Outputs - - // Use the following lines if ram output and mux can be made fast enough - - assign wb_err_o = 1'b0; // Unused for now - assign wb_rty_o = 1'b0; // Unused for now - - always @(posedge wb_clk_i) - wb_ack_o <= wb_stb_i & ~wb_ack_o; - assign wb_dat_o = buf_doa[which_buf]; - - // Use this if we can't make the RAM+MUX fast enough - // reg [31:0] wb_dat_o_reg; - // reg stb_d1; - - // always @(posedge wb_clk_i) - // begin - // wb_dat_o_reg <= buf_doa[which_buf]; - // stb_d1 <= wb_stb_i; - // wb_ack_o <= (stb_d1 & ~wb_ack_o) | (wb_we_i & wb_stb_i); - // end - //assign wb_dat_o = wb_dat_o_reg; - - mux8 #(.WIDTH(1)) - mux8_wr_ready0(.en(~write_src[0][3]),.sel(write_src[0][2:0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), - .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]), - .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),.o(wr0_ready_o)); - - mux8 #(.WIDTH(1)) - mux8_wr_full0(.en(~write_src[0][3]),.sel(write_src[0][2:0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]), - .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]), - .i5(wr_full_o[5]), .i6(wr_full_o[6]), .i7(wr_full_o[7]),.o(wr0_full_o)); - - mux8 #(.WIDTH(1)) - mux8_wr_ready1(.en(~write_src[1][3]),.sel(write_src[1][2:0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), - .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]), - .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),.o(wr1_ready_o)); - - mux8 #(.WIDTH(1)) - mux8_wr_full1(.en(~write_src[1][3]),.sel(write_src[1][2:0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]), - .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]), - .i5(wr_full_o[5]), .i6(wr_full_o[6]), .i7(wr_full_o[7]),.o(wr1_full_o)); - - mux8 #(.WIDTH(1)) - mux8_wr_ready2(.en(~write_src[2][3]),.sel(write_src[2][2:0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), - .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]), - .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),.o(wr2_ready_o)); - - mux8 #(.WIDTH(1)) - mux8_wr_full2(.en(~write_src[2][3]),.sel(write_src[2][2:0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]), - .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]), - .i5(wr_full_o[5]), .i6(wr_full_o[6]), .i7(wr_full_o[7]),.o(wr2_full_o)); - - mux8 #(.WIDTH(1)) - mux8_wr_ready3(.en(~write_src[3][3]),.sel(write_src[3][2:0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]), - .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]), - .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), .i7(wr_ready_o[7]),.o(wr3_ready_o)); - - mux8 #(.WIDTH(1)) - mux8_wr_full3(.en(~write_src[3][3]),.sel(write_src[3][2:0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]), - .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]), - .i5(wr_full_o[5]), .i6(wr_full_o[6]), .i7(wr_full_o[7]),.o(wr3_full_o)); - - mux8 #(.WIDTH(1)) - mux8_rd_sop0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), .i0(rd_sop_o[0]), .i1(rd_sop_o[1]), - .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]), - .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), .i7(rd_sop_o[7]),.o(rd0_sop_o)); - - mux8 #(.WIDTH(1)) - mux8_rd_eop0(.en(~read_src[0][3]),.sel(read_src[0][2:0]), .i0(rd_eop_o[0]), .i1(rd_eop_o[1]), - .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]), - .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), .i7(rd_eop_o[7]),.o(rd0_eop_o)); - - mux8 #(.WIDTH(32)) - mux8_rd_dat_0 (.en(~read_src[0][3]),.sel(read_src[0][2:0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]), - .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]), - .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), .i7(rd_dat_o[7]),.o(rd0_dat_o)); - - mux8 #(.WIDTH(1)) - mux8_rd_sop1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), .i0(rd_sop_o[0]), .i1(rd_sop_o[1]), - .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]), - .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), .i7(rd_sop_o[7]),.o(rd1_sop_o)); - - mux8 #(.WIDTH(1)) - mux8_rd_eop1(.en(~read_src[1][3]),.sel(read_src[1][2:0]), .i0(rd_eop_o[0]), .i1(rd_eop_o[1]), - .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]), - .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), .i7(rd_eop_o[7]),.o(rd1_eop_o)); - - mux8 #(.WIDTH(32)) - mux8_rd_dat_1 (.en(~read_src[1][3]),.sel(read_src[1][2:0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]), - .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]), - .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), .i7(rd_dat_o[7]),.o(rd1_dat_o)); - - mux8 #(.WIDTH(1)) - mux8_rd_sop2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), .i0(rd_sop_o[0]), .i1(rd_sop_o[1]), - .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]), - .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), .i7(rd_sop_o[7]),.o(rd2_sop_o)); - - mux8 #(.WIDTH(1)) - mux8_rd_eop2(.en(~read_src[2][3]),.sel(read_src[2][2:0]), .i0(rd_eop_o[0]), .i1(rd_eop_o[1]), - .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]), - .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), .i7(rd_eop_o[7]),.o(rd2_eop_o)); - - mux8 #(.WIDTH(32)) - mux8_rd_dat_2 (.en(~read_src[2][3]),.sel(read_src[2][2:0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]), - .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]), - .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), .i7(rd_dat_o[7]),.o(rd2_dat_o)); - - mux8 #(.WIDTH(1)) - mux8_rd_sop3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), .i0(rd_sop_o[0]), .i1(rd_sop_o[1]), - .i2(rd_sop_o[2]), .i3(rd_sop_o[3]), .i4(rd_sop_o[4]), - .i5(rd_sop_o[5]), .i6(rd_sop_o[6]), .i7(rd_sop_o[7]),.o(rd3_sop_o)); - - mux8 #(.WIDTH(1)) - mux8_rd_eop3(.en(~read_src[3][3]),.sel(read_src[3][2:0]), .i0(rd_eop_o[0]), .i1(rd_eop_o[1]), - .i2(rd_eop_o[2]), .i3(rd_eop_o[3]), .i4(rd_eop_o[4]), - .i5(rd_eop_o[5]), .i6(rd_eop_o[6]), .i7(rd_eop_o[7]),.o(rd3_eop_o)); - - mux8 #(.WIDTH(32)) - mux8_rd_dat_3 (.en(~read_src[3][3]),.sel(read_src[3][2:0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]), - .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]), - .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), .i7(rd_dat_o[7]),.o(rd3_dat_o)); - - assign sys_int_o = (|error) | (|done); - -endmodule // buffer_pool -- cgit v1.2.3 From 29fa1be3dc307d6d9be0fc3a004213eea50e6071 Mon Sep 17 00:00:00 2001 From: Matt Ettus Date: Wed, 2 Sep 2009 16:46:06 -0700 Subject: Removed these files completely, they were for the old style of fifos --- control_lib/buffer_int.v | 0 control_lib/buffer_int_tb.v | 447 ------------------------------------------- control_lib/buffer_pool.v | 0 control_lib/buffer_pool_tb.v | 50 ----- 4 files changed, 497 deletions(-) delete mode 100644 control_lib/buffer_int.v delete mode 100644 control_lib/buffer_int_tb.v delete mode 100644 control_lib/buffer_pool.v delete mode 100644 control_lib/buffer_pool_tb.v (limited to 'control_lib/buffer_pool.v') diff --git a/control_lib/buffer_int.v b/control_lib/buffer_int.v deleted file mode 100644 index e69de29bb..000000000 diff --git a/control_lib/buffer_int_tb.v b/control_lib/buffer_int_tb.v deleted file mode 100644 index 4fb5c6710..000000000 --- a/control_lib/buffer_int_tb.v +++ /dev/null @@ -1,447 +0,0 @@ - -module buffer_int_tb (); - - reg clk = 0; - reg rst = 1; - - initial #100 rst = 0; - always #5 clk = ~clk; - - wire en, we; - wire [8:0] addr; - wire [31:0] fifo2buf, buf2fifo; - - wire [31:0] rd_dat_o; - wire rd_sop_o, rd_eop_o; - reg rd_done_i = 0, rd_error_i = 0, rd_read_i = 0; - - reg [31:0] wr_dat_i = 0; - reg wr_write_i=0, wr_done_i = 0, wr_error_i = 0; - wire wr_ready_o, wr_full_o; - - reg clear = 0, write = 0, read = 0; - reg [8:0] firstline = 0, lastline = 0; - wire [3:0] step = 1; - wire [31:0] ctrl_word = {4'b0,3'b0,clear,write,read,step,lastline,firstline}; - reg go = 0; - wire done, error; - - buffer_int buffer_int - (.clk(clk),.rst(rst), - .ctrl_word(ctrl_word),.go(go), - .done(done),.error(error), - - // Buffer Interface - .en_o(en),.we_o(we),.addr_o(addr), - .dat_to_buf(fifo2buf),.dat_from_buf(buf2fifo), - - // Write FIFO Interface - .wr_dat_i(wr_dat_i), .wr_write_i(wr_write_i), .wr_done_i(wr_done_i), .wr_error_i(wr_error_i), - .wr_ready_o(wr_ready_o), .wr_full_o(wr_full_o), - - // Read FIFO Interface - .rd_dat_o(rd_dat_o), .rd_read_i(rd_read_i), .rd_done_i(rd_done_i), .rd_error_i(rd_error_i), - .rd_sop_o(rd_sop_o), .rd_eop_o(rd_eop_o) - ); - - reg ram_en = 0, ram_we = 0; - reg [8:0] ram_addr = 0; - reg [31:0] ram_data = 0; - - ram_2port #(.DWIDTH(32),.AWIDTH(9)) ram_2port - (.clka(clk), .ena(ram_en), .wea(ram_we), .addra(ram_addr), .dia(ram_data), .doa(), - .clkb(clk), .enb(en), .web(we), .addrb(addr), .dib(fifo2buf), .dob(buf2fifo) ); - - initial - begin - @(negedge rst); - @(posedge clk); - FillRAM; - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing full read, no wait states."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(6,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing full read, 2 wait states."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(6,2); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing full read, done ON the last."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(5,2); - rd_done_i <= 1; - ReadALine; - rd_done_i <= 0; - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing partial read, 0 wait states, then nothing after last."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(3,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing partial read, 0 wait states, then done after last."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(3,0); - rd_done_i <= 1; - @(posedge clk); - rd_done_i <= 0; - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing partial read, 0 wait states, then done at same time as last."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(2,0); - rd_done_i <= 1; - ReadALine; - rd_done_i <= 0; - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing partial read, 3 wait states, then error at same time as last."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(2,3); - rd_error_i <= 1; - ReadALine; - rd_error_i <= 0; - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(5,10); - $display("Testing Reading too much, 3 wait states."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(9,3); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(500,511); - $display("Testing full read, to the end of the buffer."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(12,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(0,511); - $display("Testing full read, start to end of the buffer."); - while(!rd_sop_o) - @(posedge clk); - ReadLines(512,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(505,3); - $display("Testing full read, wraparound"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(11,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(10,15); - $display("Testing Full Write, no wait states"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(6,0,72); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(18,23); - $display("Testing Full Write, 1 wait states"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(6,0,101); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(27,40); - $display("Testing Partial Write, 0 wait states"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(6,0,201); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(35,200); - $display("Testing Partial Write, 0 wait states, then done"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(6,0,301); - wr_done_i <= 1; - @(posedge clk); - wr_done_i <= 0; - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(45,200); - $display("Testing Partial Write, 0 wait states, then done and write simultaneously"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(6,0,301); - wr_done_i <= 1; - WriteALine(400); - wr_done_i <= 0; - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(55,200); - $display("Testing Partial Write, 0 wait states, then error"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(6,0,501); - wr_error_i <= 1; - @(posedge clk); - wr_error_i <= 0; - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(0,82); - $display("Testing read after all the writes"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(83,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(508,4); - $display("Testing wraparound write"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(9,0,601); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(506,10); - $display("Reading wraparound write"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(17,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(0,511); - $display("Testing Whole Buffer write"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(512,0,1000); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(0,511); - $display("Reading Whole Buffer write"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(512,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(5,10); - $display("Testing Write Too Many"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(12,0,2000); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(0,15); - $display("Reading back Write Too Many"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(16,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferWrite(15,20); - $display("Testing Write One Less Than Full"); - while(!wr_ready_o) - @(posedge clk); - WriteLines(5,0,2000); - repeat (10) - @(posedge clk); - - ResetBuffer; - SetBufferRead(13,22); - $display("Reading back Write One Less Than Full"); - while(!rd_sop_o) - @(posedge clk); - ReadLines(10,0); - repeat (10) - @(posedge clk); - - ResetBuffer; - repeat(100) - @(posedge clk); - $finish; - end - - always @(posedge clk) - if(rd_read_i == 1'd1) - $display("READ Buffer %d, rd_sop_o %d, rd_eop_o %d", rd_dat_o, rd_sop_o, rd_eop_o); - - always @(posedge clk) - if(wr_write_i == 1'd1) - $display("WRITE Buffer %d, wr_ready_o %d, wr_full_o %d", wr_dat_i, wr_ready_o, wr_full_o); - - initial begin - $dumpfile("buffer_int_tb.vcd"); - $dumpvars(0,buffer_int_tb); - end - - task FillRAM; - begin - ram_addr <= 0; - ram_data <= 0; - @(posedge clk); - ram_en <= 1; - ram_we <= 1; - @(posedge clk); - repeat (511) - begin - ram_addr <= ram_addr + 1; - ram_data <= ram_data + 1; - ram_en <= 1; - ram_we <= 1; - @(posedge clk); - end - ram_en <= 0; - ram_we <= 0; - @(posedge clk); - $display("Filled the RAM"); - end - endtask // FillRAM - - task ResetBuffer; - begin - clear <= 1; read <= 0; write <= 0; - go <= 1; - @(posedge clk); - go <= 0; - @(posedge clk); - $display("Buffer Reset"); - end - endtask // ClearBuffer - - task SetBufferWrite; - input [8:0] start; - input [8:0] stop; - begin - clear <= 0; read <= 0; write <= 1; - firstline <= start; - lastline <= stop; - go <= 1; - @(posedge clk); - go <= 0; - @(posedge clk); - $display("Buffer Set for Write"); - end - endtask // SetBufferWrite - - task SetBufferRead; - input [8:0] start; - input [8:0] stop; - begin - clear <= 0; read <= 1; write <= 0; - firstline <= start; - lastline <= stop; - go <= 1; - @(posedge clk); - go <= 0; - @(posedge clk); - $display("Buffer Set for Read"); - end - endtask // SetBufferRead - - task ReadALine; - begin - #1 rd_read_i <= 1; - @(posedge clk); - rd_read_i <= 0; - end - endtask // ReadALine - - task ReadLines; - input [9:0] lines; - input [7:0] wait_states; - begin - $display("Read Lines: Number %d, Wait States %d",lines,wait_states); - repeat (lines) - begin - ReadALine; - repeat (wait_states) - @(posedge clk); - end - end - endtask // ReadLines - - task WriteALine; - input [31:0] value; - begin - #1 wr_write_i <= 1; - wr_dat_i <= value; - @(posedge clk); - wr_write_i <= 0; - end - endtask // WriteALine - - task WriteLines; - input [9:0] lines; - input [7:0] wait_states; - input [31:0] value; - begin - $display("Write Lines: Number %d, Wait States %d",lines,wait_states); - repeat(lines) - begin - value <= value + 1; - WriteALine(value); - repeat(wait_states) - @(posedge clk); - end - end - endtask // WriteLines - -endmodule // buffer_int_tb diff --git a/control_lib/buffer_pool.v b/control_lib/buffer_pool.v deleted file mode 100644 index e69de29bb..000000000 diff --git a/control_lib/buffer_pool_tb.v b/control_lib/buffer_pool_tb.v deleted file mode 100644 index 16741438e..000000000 --- a/control_lib/buffer_pool_tb.v +++ /dev/null @@ -1,50 +0,0 @@ - -module buffer_pool_tb(); - - wire wb_clk_i; - wire wb_rst_i; - wire wb_we_i; - wire wb_stb_i; - wire [15:0] wb_adr_i; - wire [31:0] wb_dat_i; - wire [31:0] wb_dat_o; - wire wb_ack_o; - wire wb_err_o; - wire wb_rty_o; - - wire stream_clk, stream_rst; - - wire set_stb; - wire [7:0] set_addr; - wire [31:0] set_data; - - wire [31:0] wr0_dat_i; - buffer_pool dut - (.wb_clk_i(wb_clk_i), - .wb_rst_i(wb_rst_i), - .wb_we_i(wb_we_i), - .wb_stb_i(wb_stb_i), - .wb_adr_i(wb_adr_i), - .wb_dat_i(wb_dat_i), - .wb_dat_o(wb_dat_o), - .wb_ack_o(wb_ack_o), - .wb_err_o(wb_err_o), - .wb_rty_o(wb_rty_o), - - .stream_clk(stream_clk), - .stream_rst(stream_rst), - - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - - .wr0_dat_i(wr0_dat_i), .wr0_write_i(), .wr0_done_i(), .wr0_error_i(), .wr0_ready_o(), .wr0_full_o(), - .wr1_dat_i(), .wr1_write_i(), .wr1_done_i(), .wr1_error_i(), .wr1_ready_o(), .wr1_full_o(), - .wr2_dat_i(), .wr2_write_i(), .wr2_done_i(), .wr2_error_i(), .wr2_ready_o(), .wr2_full_o(), - .wr3_dat_i(), .wr3_write_i(), .wr3_done_i(), .wr3_error_i(), .wr3_ready_o(), .wr3_full_o(), - - .rd0_dat_o(), .rd0_read_i(), .rd0_done_i(), .rd0_error_i(), .rd0_ready_o(), .rd0_empty_o(), - .rd1_dat_o(), .rd1_read_i(), .rd1_done_i(), .rd1_error_i(), .rd1_ready_o(), .rd1_empty_o(), - .rd2_dat_o(), .rd2_read_i(), .rd2_done_i(), .rd2_error_i(), .rd2_ready_o(), .rd2_empty_o(), - .rd3_dat_o(), .rd3_read_i(), .rd3_done_i(), .rd3_error_i(), .rd3_ready_o(), .rd3_empty_o() - ); - -endmodule // buffer_pool_tb -- cgit v1.2.3