|  | Commit message (Collapse) | Author | Age | Files | Lines | 
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| | This sequence is the one as described by the AD9371 user guide. | 
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| | Added set_sync_source method to set both the time and clock sources
without forcing a re-init twice. Modified the existing set_time_source
and set_clock_source methods to call into set_sync_source. | 
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| | - Fix the syntax to open mboard-regs UIO objects, and change the open()
and close() functions to be private.
- We were calling open() twice in every context manager line- once
manually, and once in __enter__. This commit corrects those usages, and
allows the context manager to fully manage the opening and closing of
UIO objects. | 
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| | Adding the following sensors:
- Catalina temperature, RSSI, and LO Lock sensors
- GPS lock, time, TPV, and SKY sensors
Co-authored-by: Brent Stapleton <brent.stapleton@ettus.com> | 
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| | Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> | 
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| | When a device is re-initialized without any changes (e.g.,
master_clock_rate, ref_clock_freq) then we can skip the initialization
sequence and move on. This shaves a significant amount of time from the
init sequence.
Fast re-init can be overridden by providing the `force_reinit=1` device
arg. | 
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| | All code relevant to initializing an N310/N300 daughterboard is moved to
its own module (mg_init.py).
No functional changes. | 
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| | - Replace mykonos finish_initialization with async version
- Replace myknonos setup_cal with async version
- Remove disable_timeout on rpc_server init() | 
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| | Reviewed-by: Martin Braun <martin.braun@ettus.com> | 
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| | No functional changes. | 
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| | The log output at level 'INFO' was pretty cluttered. This cleans up the
log messages at the higher levels. In some cases, log message typos or
capitalizations were also fixed. | 
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| | This module (and class) are, in fact, used for all N3xx-derivates so
renaming it is the more correct thing to do. | 
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| | - Fix typo in company name (missing 'a')
- Updated SPDX license identifier to version 3.0 | 
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| | Reviewed-by: Martin Braun <martin.braun@ettus.com> | 
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| | Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> | 
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| | Add axi_bitq support. In order for this to work we need several
conditions to be true:
- Updated openocd
- FPGA image with axi_bitq built in and hooked up to correct pins
- Updated overlays matching the FPGA image
- An svf file with correct max frequency <= 10MHz
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> | 
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| | Using string expression instead of passing in a total hex value.
Now user can passed in for example: init_cals=DEFAULT or
init_cals=BASIC|TX_QEC_INIT
Reviewed-by: Martin Braun <martin.braun@ettus.com> | 
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| | Updating the UIO usage in the debug functions in magnesium.py. Somehow
this didn't get updated before. | 
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| | Slot A and Slot B are different in how the JESD lanes are connected.
We now pass in different deserializer_lane_xbar config values for each slot.
Reviewed-by: Martin Braun <martin.braun@ettus.com>
Reviewed-by: Daniel Jepson <daniel.jepson@ettus.com>
Reviewed-by: Mark Meserve <mark.meserve@ni.com> | 
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| | Reviewed-by: Martin Braun <martin.braun@ettus.com> | 
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| | There was a theoretical chance otherwise that we forgot to set the
ref_clock_freq value and it set up the LMK incorrectly.
Reviewed-by: Daniel Jepson <daniel.jepson@ettus.com> | 
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| | Reviewed-by: Ashish Chaudhari <ashish.chaudhari@ettus.com>
Reviewed-by: Martin Braun <martin.braun@ettus.com> | 
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| | - add version control checks and bump to match latest core
 - add detailed mykonos reporting
 - add detailed fpga deframer reporting
 - misc cleanup
Reviewed-by: Ashish Chaudhari <ashish.chaudhari@ettus.com>
Reviewed-by: Martin Braun <martin.braun@ettus.com> | 
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| | Now checks the oldest-compat-rev register. Current rev is read out for
logging purposes.
Reviewed-by: Daniel Jepson <daniel.jepson@ettus.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com> | 
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| | According to ADI, this bit toggles a lot so ignoring it for now. | 
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| | This is a band-aid solution. | 
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| | - Magnesium: Bad formatting in DRP setup
- PeriphManagerBase: Import order
- dtoverlay: Missed default value for param | 
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| | Reviewed-by: Martin Braun <martin.braun@ettus.com> | 
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| | Reviewed-By: Martin Braun <martin.braun@ettus.com> | 
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| | For unknown revs, this now scales back to the last known rev.
Reviewed-By: Trung Tran <trung.tran@ettus.com> | 
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| | Now uses SPDX headers everywhere. | 
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| | Refactoring to use the C++-based UIO objects. The Liberio and Ethernet
objects now open the UIO before using it, and close it once done.
Reviewed-By: Martin Braun <martin.braun@ettus.com> | 
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| | - Moved nijesdcore to cores/
- Moved udev, net, dtoverlay, uio to sys_utils/
- Made all imports non-relative (except in __init__.py files)
- Removed some unnecessary imports
- Reordered some imports for Python conventions |