|  | Commit message (Collapse) | Author | Age | Files | Lines | 
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| | - Updated README with instructions on how to build using new SDK
(1.3.4 as of this change)
- Updated makefiles
- Updated memory map patch
Signed-off-by: michael-west <michael.west@ettus.com> | 
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| | The address for the serial number was off by 2 bytes, causing a bad
value in the USB descriptor.  This only occurred if the bootloader
image was loaded on the device.
Signed-off-by: michael-west <michael.west@ettus.com> | 
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| | - Adds custom bootloader code
- Refactor common functions in firmware and bootloader | 
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| | MASK_GPIO_SHDN_SW ( GPIO[52] ) should be shifted by "GPIO_SHDN_SW" but "GPIO_FX3_SCLK ".
Otherwise GPIOs of FX3 will initial GPIO_FX3_SCLK ( GPIO[53] ) as GPIO and SPI respectively. 
It will make GPIO[53] conflict between SPI and GPIO, and SHDN_SW will not work properly as a power switch. | 
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| | Change FX3 firmware for USB2 so the eob flag is always seen,
particularly on packets that are a multiple of 512 bytes
in size. | 
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| | - B2x0: FW compat number (goes with previous firmware update)
- X3x0: Max HW rev number | 
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| | - Logging in conjunction with B200 side-channel utility
  (using UART or directly over USB)
- More and better configurability, e.g. Tx voltage swing
  and DMA configuration | 
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| | Conflicts:
	firmware/fx3/b200/b200_usb_descriptors.c | 
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| | - FX3 does not respond to AD9361 firmware transaction VREQs
- FX3 does not respond to AD9361 SPI transaction VREQs
- Deleted all AD9361 firmware files
- Bumped FW compat to 6 | 
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| | - Switched to FPGA SPI engine
- Moved firmware AD9361 driver to UHD
- Bumped FW compat to 5, FPGA compat to 4
- Known Issue: AD9361 SPI rate is too slow | 
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