| Commit message (Collapse) | Author | Age | Files | Lines |
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Conflicts:
host/include/uhd/usrp/multi_usrp.hpp
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Conflicts:
host/lib/usrp/common/ad9361_ctrl.hpp
host/lib/usrp/common/ad9361_driver/ad9361_device.h
host/lib/usrp/e300/e300_remote_codec_ctrl.hpp
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When the LO is tuned it changes the frequency on both channels. The frequency value read back for the first channel was not updated when the LO frequency for the other channel was tuned to a different value.
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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The sc16-sc16 wire to host type converter is effectively an I/Q swap
or 16-bit byteswap for little and big endian cases respectively. This
implmentation is a subset of fc32 and fc64 converters without the
floating point portion and scaling.
The resulting byte ordering is as follows:
-----------------
| A | B | C | D | Wire
-----------------
0 1 2 3
-----------------
| C | D | A | B | Litte-endian
-----------------
0 1 2 3
-----------------
| B | A | D | C | Big-endian
-----------------
0 1 2 3
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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The sc16-sc16 wire to host type converter is effectively an I/Q swap
or 16-bit byteswap for little and big endian cases respectively. This
implmentation is a subset of fc32 and fc64 converters without the
floating point portion and scaling.
The resulting byte ordering is as follows:
-----------------
| A | B | C | D | Wire
-----------------
0 1 2 3
-----------------
| C | D | A | B | Litte-endian
-----------------
0 1 2 3
-----------------
| B | A | D | C | Big-endian
-----------------
0 1 2 3
Signed-off-by: Tom Tsou <tom.tsou@ettus.com>
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Conflicts:
fpga-src
host/CMakeLists.txt
host/cmake/Modules/UHDVersion.cmake
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- Updated fpga-src
- Updated version strings
- Updated images package
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Max rate is now set to 53248000, allowing for more than 8MS/s,
which is closer to the actual value that USB2 can handle.
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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The example code given in the docs would set the wrong bit.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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This is a change from behaviour so far. Before the GPS was only
on while UHD is running. This behaviour was confusing users,
and didn't match our other devices.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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Before the device time wasn't set for E310 on initialization.
This will allow 'query_gpsdo_sensors' to pass if gps has lock.
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
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- Affect USRP X3x0 and USRP E310
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Conflicts:
fpga-src
host/CMakeLists.txt
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The actual FPGA manual pages are in the FPGA repository.
Only if the submodule is checked out will it build the manual
pages.
If the submodule is not checked out, it will create a link to
the FPGA manual hosted online.
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When auto tick rate is used, and the sampling rate exceeds the
limits, throw an error instead of coercing to the default rate.
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