diff options
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/top/B100/u1plus_core.v | 9 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e_core.v | 9 |
2 files changed, 8 insertions, 10 deletions
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index d949d7f1f..e0016a2df 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -56,8 +56,6 @@ module u1plus_core localparam SR_CLEAR_TX_FIFO = 62; // 1 reg localparam SR_GLOBAL_RESET = 63; // 1 reg - wire [7:0] COMPAT_NUM = 8'd5; - wire wb_clk = clk_fpga; wire wb_rst, global_reset; @@ -310,7 +308,6 @@ module u1plus_core localparam REG_RX_FRAMELEN = 7'd10; // in localparam REG_TX_FRAMELEN = 7'd12; // out localparam REG_XFER_RATE = 7'd14; // out - localparam REG_COMPAT = 7'd16; // in always @(posedge wb_clk) if(wb_rst) @@ -343,7 +340,6 @@ module u1plus_core assign s0_dat_miso = (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : (s0_adr[6:0] == REG_TEST) ? reg_test : - (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } : 16'hBEEF; assign s0_ack = s0_stb & s0_cyc; @@ -398,6 +394,9 @@ module u1plus_core // ///////////////////////////////////////////////////////////////////////// // Readback mux 32 -- Slave #7 + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = {16'd8, 16'd0}; //major, minor + wire [31:0] reg_test32; setting_reg #(.my_addr(SR_REG_TEST32)) sr_reg_test32 @@ -411,7 +410,7 @@ module u1plus_core .word00(vita_time[63:32]), .word01(vita_time[31:0]), .word02(vita_time_pps[63:32]), .word03(vita_time_pps[31:0]), .word04(reg_test32), .word05(gpio_readback), - .word06(32'b0), .word07(32'b0), + .word06(compat_num), .word07(32'b0), .word08(32'b0), .word09(32'b0), .word10(32'b0), .word11(32'b0), .word12(32'b0), .word13(32'b0), diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index f4b000cb9..9126c7bc0 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -60,8 +60,6 @@ module u1e_core localparam SR_CLEAR_TX_FIFO = 62; // 1 reg localparam SR_GLOBAL_RESET = 63; // 1 reg - wire [7:0] COMPAT_NUM = 8'd6; - wire wb_clk = clk_fpga; wire wb_rst, global_reset; @@ -309,7 +307,6 @@ module u1e_core localparam REG_CGEN_ST = 7'd6; // in localparam REG_TEST = 7'd8; // out localparam REG_XFER_RATE = 7'd14; // out - localparam REG_COMPAT = 7'd16; // in always @(posedge wb_clk) if(wb_rst) @@ -338,7 +335,6 @@ module u1e_core assign s0_dat_miso = (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl : (s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} : (s0_adr[6:0] == REG_TEST) ? reg_test : - (s0_adr[6:0] == REG_COMPAT) ? { 8'd0, COMPAT_NUM } : 16'hBEEF; assign s0_ack = s0_stb & s0_cyc; @@ -432,6 +428,9 @@ module u1e_core // ///////////////////////////////////////////////////////////////////////// // Readback mux 32 -- Slave #7 + //compatibility number -> increment when the fpga has been sufficiently altered + localparam compat_num = {16'd8, 16'd0}; //major, minor + wire [31:0] reg_test32; //this setting reg is persistent across resets, to check for fpga loaded @@ -446,7 +445,7 @@ module u1e_core .word00(vita_time[63:32]), .word01(vita_time[31:0]), .word02(vita_time_pps[63:32]), .word03(vita_time_pps[31:0]), .word04(reg_test32), .word05(err_status), - .word06(32'b0), .word07(32'b0), + .word06(compat_num), .word07(32'b0), .word08(32'b0), .word09(32'b0), .word10(32'b0), .word11(32'b0), .word12(32'b0), .word13(32'b0), |