diff options
Diffstat (limited to 'usrp2')
32 files changed, 512 insertions, 1586 deletions
diff --git a/usrp2/extram/.gitignore b/usrp2/extram/.gitignore deleted file mode 100644 index 7fc71ccb6..000000000 --- a/usrp2/extram/.gitignore +++ /dev/null @@ -1 +0,0 @@ -/a.out diff --git a/usrp2/extram/Makefile.srcs b/usrp2/extram/Makefile.srcs deleted file mode 100644 index 90be02142..000000000 --- a/usrp2/extram/Makefile.srcs +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright 2010 Ettus Research LLC -# - -################################################## -# Extram Sources -################################################## -EXTRAM_SRCS = $(abspath $(addprefix $(BASE_DIR)/../extram/, \ -wb_zbt16_b.v \ -)) diff --git a/usrp2/extram/extram_interface.v b/usrp2/extram/extram_interface.v deleted file mode 100644 index 7554592ba..000000000 --- a/usrp2/extram/extram_interface.v +++ /dev/null @@ -1,53 +0,0 @@ - -// Temporary buffer pool storage, mostly useful for pre-generated data streams or -// for making more space to juggle packets in case of eth frames coming out of order - -module extram_interface - (input clk, input rst, - input set_stb, input [7:0] set_addr, input [31:0] set_data, - - // Buffer pool interfaces - input [31:0] rd_dat_i, output rd_read_o, output rd_done_o, output rd_error_o, - input rd_sop_i, input rd_eop_i, - output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output wr_error_o, - input wr_ready_i, input wr_full_i, - - // RAM Interface - inout [17:0] RAM_D, - output [18:0] RAM_A, - output RAM_CE1n, - output RAM_CENn, - input RAM_CLK, - output RAM_WEn, - output RAM_OEn, - output RAM_LDn ); - - // Command format -- - // Read/_Write , start address[17:0] - wire [18:0] cmd_in; - wire cmd_stb, store_wr_cmd, store_rd_cmd, read_wr_cmd, read_rd_cmd; - wire empty_wr_cmd, empty_rd_cmd, full_wr_cmd, full_rd_cmd; - - // Dummy logic - assign RAM_OEn = 1; - - setting_reg #(.my_addr(0)) - sr_ram_cmd (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out(cmd_in),.changed(cmd_stb)); - - reg cmd_stb_d1; - always @(posedge clk) cmd_stb_d1 <= cmd_stb; - assign store_wr_cmd = ~cmd_in[18] & cmd_stb & ~cmd_stb_d1; - assign store_rd_cmd = cmd_in[18] & cmd_stb & ~cmd_stb_d1; - - shortfifo #(.WIDTH(19)) wr_cmd_fifo - (.clk(clk),.rst(rst),.clear(1'b0), - .datain(cmd_in), .write(store_wr_cmd), .full(full_wr_cmd), - .dataout(), .read(read_wr_cmd), .empty(empty_wr_cmd) ); - - shortfifo #(.WIDTH(19)) rd_cmd_fifo - (.clk(clk),.rst(rst),.clear(1'b0), - .datain(cmd_in), .write(store_rd_cmd), .full(full_rd_cmd), - .dataout(), .read(read_rd_cmd), .empty(empty_rd_cmd) ); - -endmodule // extram_interface diff --git a/usrp2/extram/extram_wb.v b/usrp2/extram/extram_wb.v deleted file mode 100644 index c8428783a..000000000 --- a/usrp2/extram/extram_wb.v +++ /dev/null @@ -1,146 +0,0 @@ - -module extram_wb - #(parameter PAGE_SIZE = 10, - parameter ADDR_WIDTH = 16) - (input clk, input rst, - input wb_clk, input wb_rst, - input cyc_i, input stb_i, - input [ADDR_WIDTH-1:0] adr_i, - input we_i, - input [31:0] dat_i, - output reg [31:0] dat_o, - output reg ack_o, - - inout [17:0] RAM_D, - output [PAGE_SIZE-2:0] RAM_A, - output RAM_CE1n, output RAM_CENn, - output RAM_CLK, output RAM_WEn, - output RAM_OEn, output RAM_LDn ); - - wire read_acc = stb_i & cyc_i & ~we_i; - wire write_acc = stb_i & cyc_i & we_i; - wire acc = stb_i & cyc_i; - - assign RAM_CLK = ~wb_clk; // 50 MHz for now, eventually should be 200 MHz - assign RAM_LDn = 0; // No burst for now - assign RAM_CENn = 0; // Use CE1n as our main CE - - reg [PAGE_SIZE-2:1] RAM_addr_reg; - always @(posedge wb_clk) - if(acc) - RAM_addr_reg[PAGE_SIZE-2:1] <= adr_i[PAGE_SIZE-1:2]; - assign RAM_A[PAGE_SIZE-2:1] = RAM_addr_reg; - - reg [31:0] ram_out; - always @(posedge wb_clk) - if(write_acc) - ram_out <= dat_i; - - // RAM access state machine - localparam RAM_idle = 0; - localparam RAM_read_1 = 1; - localparam RAM_read_2 = 2; - localparam RAM_read_3 = 3; - localparam RAM_read_4 = 4; - localparam RAM_write_1 = 6; - localparam RAM_write_2 = 7; - localparam RAM_write_3 = 8; - localparam RAM_write_4 = 9; - - reg myOE = 0; - reg RAM_OE = 0; - reg RAM_WE = 0; - reg RAM_EN = 0; - reg RAM_A0_reg; - reg [3:0] RAM_state; - - always @(posedge wb_clk) - if(wb_rst) - begin - RAM_state <= RAM_idle; - myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; - end - else - case(RAM_state) - RAM_idle : - if(read_acc & ~ack_o) - begin - RAM_state <= RAM_read_1; - myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 1; RAM_A0_reg <= 0; - end - else if(write_acc & ~ack_o) - begin - RAM_state <= RAM_write_1; - myOE <= 0; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 0; - end - else - begin - myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; - end - RAM_read_1 : - begin - RAM_state <= RAM_read_2; - myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 1; RAM_A0_reg <= 1; - end - RAM_read_2 : - begin - RAM_state <= RAM_read_3; - myOE <= 0; RAM_OE <= 1; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; - end - RAM_read_3 : - begin - RAM_state <= RAM_read_4; - myOE <= 0; RAM_OE <= 1; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; - end - RAM_read_4 : - begin - RAM_state <= RAM_idle; - myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; - end - RAM_write_1 : - begin - RAM_state <= RAM_write_2; - myOE <= 1; RAM_OE <= 0; RAM_WE <= 1; RAM_EN <= 1; RAM_A0_reg <= 1; - end - RAM_write_2 : - begin - RAM_state <= RAM_write_3; - myOE <= 1; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; - end - RAM_write_3 : - begin - RAM_state <= RAM_write_4; - myOE <= 1; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; - end - RAM_write_4 : - begin - RAM_state <= RAM_idle; - myOE <= 0; RAM_OE <= 0; RAM_WE <= 0; RAM_EN <= 0; RAM_A0_reg <= 0; - end - default : RAM_state <= RAM_idle; - endcase // case(RAM_state) - - assign RAM_A[0] = RAM_A0_reg; - assign RAM_WEn = ~RAM_WE; // ((RAM_state==RAM_write_1)||(RAM_state==RAM_write_2)); - assign RAM_OEn = ~RAM_OE; - assign RAM_CE1n = ~RAM_EN; // Active low (RAM_state != RAM_idle); - - assign RAM_D[17:16] = 2'bzz; - assign RAM_D[15:0] = myOE ? ((RAM_state==RAM_write_2)?ram_out[15:0]:ram_out[31:16]) - : 16'bzzzz_zzzz_zzzz_zzzz; - - always @(posedge wb_clk) - if(RAM_state == RAM_read_3) - dat_o[15:0] <= RAM_D[15:0]; - else - dat_o[31:16] <= RAM_D[15:0]; - - always @(posedge wb_clk) - if(wb_rst) - ack_o <= 0; - else if((RAM_state == RAM_write_4)||(RAM_state == RAM_read_4)) - ack_o <= 1; - else - ack_o <= 0; - -endmodule // extram_wb diff --git a/usrp2/extram/wb_zbt16_b.v b/usrp2/extram/wb_zbt16_b.v deleted file mode 100644 index d93e21c99..000000000 --- a/usrp2/extram/wb_zbt16_b.v +++ /dev/null @@ -1,63 +0,0 @@ - -module wb_zbt16_b - (input clk, - input rst, - // Wishbone bus A, highest priority, with prefetch - input [19:0] wb_adr_i, - input [15:0] wb_dat_i, - output reg [15:0] wb_dat_o, - input [ 1:0] wb_sel_i, - input wb_cyc_i, - input wb_stb_i, - output reg wb_ack_o, - input wb_we_i, - // Memory connection - output sram_clk, - output [18:0] sram_a, - inout [15:0] sram_d, - output sram_we, - output [ 1:0] sram_bw, - output sram_adv, - output sram_ce, - output sram_oe, - output sram_mode, - output sram_zz - ); - - assign sram_clk = ~clk; - //assign sram_oe = 1'b0; - assign sram_ce = 1'b0; - assign sram_adv = 1'b0; - assign sram_mode = 1'b0; - assign sram_zz = 1'b0; - assign sram_bw = 2'b0; - - // need to drive wb_dat_o, wb_ack_o, - // sram_a, sram_d, sram_we - wire myOE; - assign sram_d = myOE ? wb_dat_i : 16'bzzzz; - assign sram_a = wb_adr_i[19:1]; - - reg read_d1, read_d2, read_d3, write_d1, write_d2, write_d3; - wire acc = wb_cyc_i & wb_stb_i; - wire read_acc = wb_cyc_i & wb_stb_i & ~wb_we_i & ~read_d1 & ~read_d2 & ~read_d3; - wire write_acc = wb_cyc_i & wb_stb_i & wb_we_i & ~write_d1 & ~write_d2 & ~write_d3; - - assign sram_we = ~write_acc; - assign sram_oe = ~(read_d2 | read_d3); - assign myOE = write_d1 | write_d2; - wire latch_now = read_d2; - - always @(posedge clk) - if(latch_now) - wb_dat_o <= sram_d; - - always @(posedge clk) wb_ack_o <= read_d2 | write_d2; - always @(posedge clk) read_d1 <= read_acc; - always @(posedge clk) read_d2 <= read_d1; - always @(posedge clk) read_d3 <= read_d2; - always @(posedge clk) write_d1 <= write_acc; - always @(posedge clk) write_d2 <= write_d1; - always @(posedge clk) write_d3 <= write_d2; -endmodule // wb_zbt16_b - diff --git a/usrp2/extramfifo/fifo_extram.v b/usrp2/extramfifo/fifo_extram.v deleted file mode 100644 index 4e1f40371..000000000 --- a/usrp2/extramfifo/fifo_extram.v +++ /dev/null @@ -1,188 +0,0 @@ - -// Everything on sram_clk - -module fifo_extram - (input reset, input clear, - input [17:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, input [15:0] occ_in, - output [17:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, input [15:0] space_in, - input sram_clk, output [18:0] sram_a, inout [17:0] sram_d, output sram_we, - output [1:0] sram_bw, output sram_adv, output sram_ce, output sram_oe, - output sram_mode, output sram_zz); - - localparam AWIDTH = 19; // 1 MB in x18 - localparam RAMSIZE = ((1<<AWIDTH) - 1); - - wire do_store, do_retrieve; - reg [1:0] do_store_del, do_retr_del; - - reg [AWIDTH-1:0] addr_retrieve, addr_store; - always @(posedge sram_clk) - if(reset | clear) - addr_retrieve <= 0; - else if (do_retrieve) - addr_retrieve <= addr_retrieve + 1; - - always @(posedge sram_clk) - if(reset | clear) - addr_store <= 0; - else if(do_store) - addr_store <= addr_store + 1; - - //wire [AWIDTH-1:0] fullness = (addr_store - addr_retrieve); - reg [AWIDTH-1:0] fullness; - always @(posedge sram_clk) - if(reset | clear) - fullness <= 0; - else if(do_store) - fullness <= fullness + 1; - else if(do_retrieve) - fullness <= fullness - 1; - - // wire empty = (fullness == 0); - //wire full = (fullness == RAMSIZE); // 19'h7FF); - reg empty, full; - - // The math in the following functions is 'AWIDTH wide. Use - // continuous assignments to prevent the numbers from being - // promoted to 32-bit (which would make it wrap wrong). - // - wire [AWIDTH-1:0] addr_retrieve_p1, addr_store_p2; - assign addr_retrieve_p1 = addr_retrieve + 1; - assign addr_store_p2 = addr_store + 2; - - always @(posedge sram_clk) - if(reset | clear) - empty <= 1; - else if(do_store) - empty <= 0; - else if(do_retrieve & (/*(addr_retrieve + 1)*/ addr_retrieve_p1 == addr_store)) - empty <= 1; - - always @(posedge sram_clk) - if(reset | clear) - full <= 0; - else if(do_retrieve) - full <= 0; - else if(do_store & (/*(addr_store+2)*/ addr_store_p2 == addr_retrieve)) - full <= 1; - - reg can_store; - always @* - if(full | ~src_rdy_i) - can_store <= 0; - else if(do_store_del == 0) - can_store <= 1; - else if((do_store_del == 1) || (do_store_del == 2)) - can_store <= (occ_in > 1); - else - can_store <= (occ_in > 2); - - reg can_retrieve; - always @* - if(empty | ~dst_rdy_i) - can_retrieve <= 0; - else if(do_retr_del == 0) - can_retrieve <= 1; - else if((do_retr_del == 1) || (do_retr_del == 2)) - can_retrieve <= (space_in > 1); - else - can_retrieve <= (space_in > 2); - - reg [1:0] state; - localparam IDLE_STORE_NEXT = 0; - localparam STORE = 1; - localparam IDLE_RETR_NEXT = 2; - localparam RETRIEVE = 3; - - reg [7:0] countdown; - wire countdown_done = (countdown == 0); - - localparam CYCLE_SIZE = 6; - - assign do_store = can_store & (state == STORE); - assign do_retrieve = can_retrieve & (state == RETRIEVE); - always @(posedge sram_clk) - if(reset) - do_store_del <= 0; - else - do_store_del <= {do_store_del[0],do_store}; - - always @(posedge sram_clk) - if(reset) - do_retr_del <= 0; - else - do_retr_del <= {do_retr_del[0],do_retrieve}; - - always @(posedge sram_clk) - if(reset | clear) - begin - state <= IDLE_STORE_NEXT; - countdown <= 0; - end - else - case(state) - IDLE_STORE_NEXT : - if(can_store) - begin - state <= STORE; - countdown <= CYCLE_SIZE; - end - else if(can_retrieve) - begin - state <= RETRIEVE; - countdown <= CYCLE_SIZE; - end - STORE : - if(~can_store | (can_retrieve & countdown_done)) - state <= IDLE_RETR_NEXT; - else if(~countdown_done) - countdown <= countdown - 1; - IDLE_RETR_NEXT : - if(can_retrieve) - begin - state <= RETRIEVE; - countdown <= CYCLE_SIZE; - end - else if(can_store) - begin - state <= STORE; - countdown <= CYCLE_SIZE; - end - RETRIEVE : - if(~can_retrieve | (can_store & countdown_done)) - state <= IDLE_STORE_NEXT; - else if(~countdown_done) - countdown <= countdown - 1; - endcase // case (state) - - // RAM wires - assign sram_bw = 0; - assign sram_adv = 0; - assign sram_mode = 0; - assign sram_zz = 0; - assign sram_ce = 0; - - assign sram_a = (state==STORE) ? addr_store : addr_retrieve; - assign sram_we = ~do_store; - assign sram_oe = ~do_retr_del[1]; - assign my_oe = do_store_del[1] & sram_oe; - assign sram_d = my_oe ? datain : 18'bz; - - // FIFO wires - assign dataout = sram_d; - assign src_rdy_o = do_retr_del[1]; - assign dst_rdy_o = do_store_del[1]; - -endmodule // fifo_extram - - - //wire have_1 = (fullness == 1); - //wire have_2 = (fullness == 2); - //wire have_atleast_1 = ~empty; - //wire have_atleast_2 = ~(empty | have_1); - //wire have_atleast_3 = ~(empty | have_1 | have_2); - //wire full_minus_1 = (fullness == (RAMSIZE-1)); // 19'h7FE); - //wire full_minus_2 = (fullness == (RAMSIZE-2)); // 19'h7FD); - //wire spacefor_atleast_1 = ~full; - //wire spacefor_atleast_2 = ~(full | full_minus_1); - //wire spacefor_atleast_3 = ~(full | full_minus_1 | full_minus_2); diff --git a/usrp2/extramfifo/fifo_extram36.v b/usrp2/extramfifo/fifo_extram36.v deleted file mode 100644 index 29342fdc4..000000000 --- a/usrp2/extramfifo/fifo_extram36.v +++ /dev/null @@ -1,47 +0,0 @@ - -// 18 bit interface means we either can't handle errors or can't handle odd lengths -// unless we go to heroic measures - -module fifo_extram36 - (input clk, input reset, input clear, - input [35:0] datain, input src_rdy_i, output dst_rdy_o, output [15:0] space, - output [35:0] dataout, output src_rdy_o, input dst_rdy_i, output [15:0] occupied, - input sram_clk, output [18:0] sram_a, inout [17:0] sram_d, output sram_we, - output [1:0] sram_bw, output sram_adv, output sram_ce, output sram_oe, output sram_mode, - output sram_zz); - - wire [17:0] f18_data_1, f18_data_2, f18_data_3, f18_data_4; - wire f18_src_rdy_1, f18_dst_rdy_1, f18_src_rdy_2, f18_dst_rdy_2; - wire f18_src_rdy_3, f18_dst_rdy_3, f18_src_rdy_4, f18_dst_rdy_4; - - fifo36_to_fifo18 f36_to_f18 - (.clk(clk), .reset(reset), .clear(clear), - .f36_datain(datain), .f36_src_rdy_i(src_rdy_i), .f36_dst_rdy_o(dst_rdy_o), - .f18_dataout(f18_data_1), .f18_src_rdy_o(f18_src_rdy_1), .f18_dst_rdy_i(f18_dst_rdy_1) ); - - wire [15:0] f1_occ, f2_space; - - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) fifo_2clock_in - (.wclk(clk), .datain(f18_data_1), .src_rdy_i(f18_src_rdy_1), .dst_rdy_o(f18_dst_rdy_1), .space(), - .rclk(sram_clk), .dataout(f18_data_2), .src_rdy_o(f18_src_rdy_2), .dst_rdy_i(f18_dst_rdy_2), .short_occupied(f1_occ), - .arst(reset) ); - - fifo_extram fifo_extram - (.reset(reset), .clear(clear), - .datain(f18_data_2), .src_rdy_i(f18_src_rdy_2), .dst_rdy_o(f18_dst_rdy_2), .space(), .occ_in(f1_occ), - .dataout(f18_data_3), .src_rdy_o(f18_src_rdy_3), .dst_rdy_i(f18_dst_rdy_3), .occupied(), .space_in(f2_space), - .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we), - .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe), - .sram_mode(sram_mode), .sram_zz(sram_zz)); - - fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) fifo_2clock_out - (.wclk(sram_clk), .datain(f18_data_3), .src_rdy_i(f18_src_rdy_3), .dst_rdy_o(f18_dst_rdy_3), .short_space(f2_space), - .rclk(clk), .dataout(f18_data_4), .src_rdy_o(f18_src_rdy_4), .dst_rdy_i(f18_dst_rdy_4), .occupied(), - .arst(reset) ); - - fifo18_to_fifo36 f18_to_f36 - (.clk(clk), .reset(reset), .clear(clear), - .f18_datain(f18_data_4), .f18_src_rdy_i(f18_src_rdy_4), .f18_dst_rdy_o(f18_dst_rdy_4), - .f36_dataout(dataout), .f36_src_rdy_o(src_rdy_o), .f36_dst_rdy_i(dst_rdy_i) ); - -endmodule // fifo_extram36 diff --git a/usrp2/extramfifo/fifo_extram36_tb.build b/usrp2/extramfifo/fifo_extram36_tb.build deleted file mode 100755 index ac9369758..000000000 --- a/usrp2/extramfifo/fifo_extram36_tb.build +++ /dev/null @@ -1 +0,0 @@ -iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram36_tb fifo_extram36_tb.v diff --git a/usrp2/extramfifo/fifo_extram36_tb.v b/usrp2/extramfifo/fifo_extram36_tb.v deleted file mode 100644 index e5f8cef4c..000000000 --- a/usrp2/extramfifo/fifo_extram36_tb.v +++ /dev/null @@ -1,475 +0,0 @@ -`timescale 1ns/1ns - -module fifo_extram36_tb(); - - reg clk = 0; - reg sram_clk = 0; - reg rst = 1; - reg clear = 0; - - reg Verbose = 0; // - integer ErrorCount = 0; - - initial #1000 rst = 0; -// always #125 clk = ~clk; - task task_CLK; - reg [7:0] ran; - begin - while (1) begin - ran = $random; - if (ran[1]) - #62 clk = ~clk; - else - #63 clk = !clk; - end - end - endtask // task_CLK - initial task_CLK; - -// always #100 sram_clk = ~sram_clk; - task task_SSRAM_clk; - reg [7:0] ran; - begin - while (1) begin - ran = $random; - if (ran[0]) - #49 sram_clk = ~sram_clk; - else - #51 sram_clk = ~sram_clk; - end - end - endtask // task_SSRAM_clk - initial task_SSRAM_clk; - - reg [31:0] f36_data = 32'hX; - reg [1:0] f36_occ = 0; - reg f36_sof = 0, f36_eof = 0; - - wire [35:0] f36_in = {1'b0,f36_occ,f36_eof,f36_sof,f36_data}; - reg src_rdy_f36i = 0; - wire dst_rdy_f36i; - - wire [35:0] f36_out; - wire src_rdy_f36o; - reg dst_rdy_f36o = 0; - - wire [17:0] sram_d; - wire [18:0] sram_a; - wire [1:0] sram_bw; - wire sram_we, sram_adv, sram_ce, sram_oe, sram_mode, sram_zz; - - reg [31:0] ScoreBoard [524288:0]; - reg [18:0] put_index = 0; - reg [18:0] get_index = 0; - -// integer put_index = 0; -// integer get_index = 0; - - wire [15:0] DUT_space, DUT_occupied; - - fifo_extram36 fifo_extram36 - (.clk(clk), .reset(rst), .clear(clear), - .datain(f36_in), .src_rdy_i(src_rdy_f36i), .dst_rdy_o(dst_rdy_f36i), .space(DUT_space), - .dataout(f36_out), .src_rdy_o(src_rdy_f36o), .dst_rdy_i(dst_rdy_f36o), .occupied(DUT_occupied), - .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we), - .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe), - .sram_mode(sram_mode), .sram_zz(sram_zz)); - -`define idt 1 -`ifdef idt - wire [15:0] dummy16; - wire [1:0] dummy2; - - idt71v65603s150 - ram_model(.A(sram_a[17:0]), - .adv_ld_(sram_adv), // advance (high) / load (low) - .bw1_(0), .bw2_(0), .bw3_(0), .bw4_(0), // byte write enables (low) - .ce1_(0), .ce2(1), .ce2_(0), // chip enables - .cen_(sram_ce), // clock enable (low) - .clk(sram_clk), // clock - .IO({dummy16,sram_d[15:0]}), - .IOP({dummy2,sram_d[17:16]}), // data bus - .lbo_(sram_mode), // linear burst order (low) - .oe_(sram_oe), // output enable (low) - .r_w_(sram_we)); // read (high) / write (low) -`else - cy1356 ram_model(.d(sram_d),.clk(~sram_clk),.a(sram_a), - .bws(2'b00),.we_b(sram_we),.adv_lb(sram_adv), - .ce1b(0),.ce2(1),.ce3b(0), - .oeb(sram_oe),.cenb(sram_ce),.mode(sram_mode) ); -`endif - - task task_SSRAMMonitor; - reg last_mode; - reg last_clock; - reg last_load; - reg [18:0] sram_addr; - - begin - last_mode = 1'bX; - last_clock = 1'bX; - last_load = 1'bX; - - @ (posedge Verbose); - $dumpvars(0,fifo_extram36_tb); - - $display("%t:%m\t*** Task Started",$time); - while (1) @ (posedge sram_clk) begin - if (sram_mode !== last_mode) begin - $display("%t:%m\tSSRAM mode: %b",$time,sram_mode); - last_mode = sram_mode; - end - if (sram_adv !== last_load) begin - $display("%t:%m\tSSRAM adv/load: %b",$time,sram_adv); - last_load = sram_adv; - end - if (sram_ce !== last_clock) begin - $display("%t:%m\tSSRAM clock enable: %b",$time,sram_ce); - last_clock = sram_ce; - end - if (sram_ce == 1'b0) begin - if (sram_adv == 1'b0) begin -// $display("%t:%m\tSSRAM Address Load A=%h",$time,sram_a); - sram_addr = sram_a; - end else begin - sram_addr = sram_addr + 1; - end - if (sram_oe == 1'b0) begin - $display("%t:%m\tSSRAM Read Cycle A=%h(%h), D=%o",$time,sram_addr-2,sram_a,sram_d); - end - if (sram_we == 1'b0) begin - $display("%t:%m\tSSRAM Write Cycle A=%h(%h), D=%o",$time,sram_addr-2,sram_a,sram_d); - end - if ((sram_we == 1'b0) && (sram_oe == 1'b0)) begin - $display("%t:%m\t*** ERROR: _oe and _we both active",$time); - end - - end // if (sram_ce == 1'b0) - - end // always @ (posedge sram_clk) - end - endtask // task_SSRAMMonitor - - task ReadFromFIFO36; - begin - $display("%t: Read from FIFO36",$time); - #1 dst_rdy_f36o <= 1; - while(1) - begin - while(~src_rdy_f36o) - @(posedge clk); - $display("%t: Read: %h>",$time,f36_out); - @(posedge clk); - end - end - endtask // ReadFromFIFO36 - - initial dst_rdy_f36o = 0; - - task task_ReadFIFO36; - reg [7:0] ran; - begin - $display("%t:%m\t*** Task Started",$time); - while (1) begin - // Read on one of four clocks - #5 dst_rdy_f36o <= 1; - @(posedge clk); - if (src_rdy_f36o) begin - if (f36_out[31:0] != ScoreBoard[get_index]) begin - $display("%t:%m\tFIFO Get Error: R:%h, E:%h (%h)",$time,f36_out[31:0],ScoreBoard[get_index],get_index); - ErrorCount = ErrorCount + 1; - end else begin - if (Verbose) - $display("%t:%m\t(%5h) %o>",$time,get_index,f36_out); - end - get_index = get_index+1; - end else begin - if (ErrorCount >= 192) - $finish; - end // else: !if(src_rdy_f36o) - - #10; - ran = $random; - if (ran[2:0] != 3'b000) begin - dst_rdy_f36o <= 0; - if (ran[2] != 1'b0) begin - @(posedge clk); - @(posedge clk); - @(posedge clk); - end - if (ran[1] != 1'b0) begin - @(posedge clk); - @(posedge clk); - end - if (ran[0] != 1'b0) begin - @(posedge clk); - end - end - end // while (1) - end - - endtask // task_ReadFIFO36 - - - reg [15:0] count; - - task PutPacketInFIFO36; - input [31:0] data_start; - input [31:0] data_len; - - begin - count = 4; - src_rdy_f36i = 1; - f36_data = data_start; - f36_sof = 1; - f36_eof = 0; - f36_occ = 0; - - $display("%t: Put Packet in FIFO36",$time); - while(~dst_rdy_f36i) - #1; //@(posedge clk); - @(posedge clk); - - $display("%t: <%h PPI_FIFO36: Entered First Line",$time,f36_data); - f36_sof <= 0; - while(count+4 < data_len) - begin - f36_data = f36_data + 32'h01010101; - count = count + 4; - while(~dst_rdy_f36i) - #1; //@(posedge clk); - @(posedge clk); - $display("%t: <%h PPI_FIFO36: Entered New Line",$time,f36_data); - end - f36_data <= f36_data + 32'h01010101; - f36_eof <= 1; - if(count + 4 == data_len) - f36_occ <= 0; - else if(count + 3 == data_len) - f36_occ <= 3; - else if(count + 2 == data_len) - f36_occ <= 2; - else - f36_occ <= 1; - while(~dst_rdy_f36i) - @(posedge clk); - @(posedge clk); - f36_occ <= 0; - f36_eof <= 0; - f36_data <= 0; - src_rdy_f36i <= 0; - $display("%t: <%h PPI_FIFO36: Entered Last Line",$time,f36_data); - end - endtask // PutPacketInFIFO36 - - task task_WriteFIFO36; - integer i; - reg [7:0] ran; - - begin - f36_data = 32'bX; - if (rst != 1'b0) - @ (negedge rst); - $display("%t:%m\t*** Task Started",$time); - #10; - src_rdy_f36i = 1; - f36_data = $random; - for (i=0; i<64; i=i+0 ) begin - @ (posedge clk) ; - if (dst_rdy_f36i) begin - if (Verbose) - $display("%t:%m\t(%5h) %o<",$time,put_index,f36_in); - ScoreBoard[put_index] = f36_in[31:0]; - put_index = put_index + 1; - #5; - f36_data = $random; - i = i + 1; - end - ran = $random; - if (ran[1:0] != 2'b00) begin - @ (negedge clk); - src_rdy_f36i = 0; - #5; - @ (negedge clk) ; - src_rdy_f36i = 1; - end - end - src_rdy_f36i = 0; - f36_data = 32'bX; -// if (put_index > 19'h3ff00) -// Verbose = 1'b1; - - end - endtask // task_WriteFIFO36 - - initial $dumpfile("fifo_extram36_tb.vcd"); -// initial $dumpvars(0,fifo_extram36_tb); - initial $timeformat(-9, 0, " ns", 10); - initial task_SSRAMMonitor; - - initial - begin - @(negedge rst); - #40000; - @(posedge clk); - @(posedge clk); - @(posedge clk); - @(posedge clk); -// ReadFromFIFO36; - task_ReadFIFO36; - - end - - integer i; - - initial - begin - @(negedge rst); - @(posedge clk); - @(posedge clk); - @(posedge clk); - task_WriteFIFO36; - @(posedge clk); - @(posedge clk); - @(posedge clk); -// PutPacketInFIFO36(32'hA0B0C0D0,12); - @(posedge clk); - @(posedge clk); - #10000; - @(posedge clk); -// PutPacketInFIFO36(32'hE0F0A0B0,36); - @(posedge clk); - @(posedge clk); - task_WriteFIFO36; - @(posedge clk); - @(posedge clk); - #10000; - @(posedge clk); - @(posedge clk); - task_WriteFIFO36; -// @(posedge clk); -// #30000; -// @(posedge clk); -// @(posedge clk); - task_WriteFIFO36; -// @(posedge clk); -// #30000; -// @(posedge clk); -// @(posedge clk); - task_WriteFIFO36; -// @(posedge clk); -// #30000; -// @(posedge clk); -// @(posedge clk); - task_WriteFIFO36; - @(posedge clk); - #10000; - @(posedge clk); - @(posedge clk); - task_WriteFIFO36; - for (i=0; i<8192; i = i+1) begin - @(posedge clk); - #10000; - @(posedge clk); - @(posedge clk); - task_WriteFIFO36; - @(posedge clk); - end - -// $dumpvars(0,fifo_extram36_tb); - @(posedge clk); - task_WriteFIFO36; - @(posedge clk); - - #100000000; - $finish; - - end - - - initial - begin - @(negedge rst); - f36_occ <= 0; - repeat (100) - @(posedge clk); - src_rdy_f36i <= 1; - f36_data <= 32'h10203040; - f36_sof <= 1; - f36_eof <= 0; - @(posedge clk); - @(posedge clk); - src_rdy_f36i <= 1; - f36_data <= f36_data + 32'h01010101; - f36_sof <= 0; - f36_eof <= 0; - @(posedge clk); - @(posedge clk); - src_rdy_f36i <= 1; - f36_data <= f36_data + 32'h01010101; - f36_sof <= 0; - f36_eof <= 0; - @(posedge clk); - @(posedge clk); - src_rdy_f36i <= 1; - f36_data <= f36_data + 32'h01010101; - f36_sof <= 0; - f36_eof <= 0; - @(posedge clk); - @(posedge clk); - src_rdy_f36i <= 1; - f36_data <= f36_data + 32'h01010101; - f36_sof <= 0; - f36_eof <= 0; - @(posedge clk); - @(posedge clk); - src_rdy_f36i <= 1; - f36_data <= f36_data + 32'h01010101; - f36_sof <= 0; - f36_eof <= 0; - @(posedge clk); - @(posedge clk); - src_rdy_f36i <= 1; - f36_data <= f36_data + 32'h01010101; - f36_sof <= 0; - f36_eof <= 0; - @(posedge clk); - @(posedge clk); - src_rdy_f36i <= 1; - f36_data <= f36_data + 32'h01010101; - f36_sof <= 0; - f36_eof <= 0; - @(posedge clk); - @(posedge clk); - src_rdy_f36i <= 1; - f36_data <= f36_data + 32'h01010101; - f36_sof <= 0; - f36_eof <= 0; - @(posedge clk); - @(posedge clk); - src_rdy_f36i <= 1; - f36_data <= f36_data + 32'h01010101; - f36_sof <= 0; - f36_eof <= 0; - @(posedge clk); - @(posedge clk); - src_rdy_f36i <= 1; - f36_data <= f36_data + 32'h01010101; - f36_sof <= 0; - f36_eof <= 0; - @(posedge clk); - @(posedge clk); - src_rdy_f36i <= 1; - f36_data <= 32'h1F2F3F4F; - f36_sof <= 0; - f36_eof <= 1; - @(posedge clk); - @(posedge clk); - src_rdy_f36i <= 0; - - - - end - -// initial #500000 $finish; -endmodule // fifo_extram_tb diff --git a/usrp2/extramfifo/fifo_extram_tb.build b/usrp2/extramfifo/fifo_extram_tb.build deleted file mode 100755 index 5607c8691..000000000 --- a/usrp2/extramfifo/fifo_extram_tb.build +++ /dev/null @@ -1 +0,0 @@ -iverilog -y ../models -y . -y ../control_lib/ -y ../coregen -y ../fifo -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -o fifo_extram_tb fifo_extram_tb.v diff --git a/usrp2/extramfifo/fifo_extram_tb.v b/usrp2/extramfifo/fifo_extram_tb.v deleted file mode 100644 index 73550d9ca..000000000 --- a/usrp2/extramfifo/fifo_extram_tb.v +++ /dev/null @@ -1,134 +0,0 @@ -module fifo_extram_tb(); - - reg clk = 0; - reg sram_clk = 0; - reg reset = 1; - reg clear = 0; - - initial #1000 reset = 0; - always #125 clk = ~clk; - always #100 sram_clk = ~sram_clk; - - reg [15:0] f18_data = 0; - reg f18_sof = 0, f18_eof = 0; - - wire [17:0] f18_in = {f18_eof,f18_sof,f18_data}; - reg src_rdy_f18i = 0; - wire dst_rdy_f18i; - - wire [17:0] f18_out; - wire src_rdy_f18o; - reg dst_rdy_f18o = 0; - - wire [17:0] f18_int; - wire src_rdy_f18int, dst_rdy_f18int; - - wire [17:0] sram_d; - wire [18:0] sram_a; - wire [1:0] sram_bw; - wire sram_we, sram_adv, sram_ce, sram_oe, sram_mode, sram_zz; - wire [15:0] f1_occ; - - fifo_short #(.WIDTH(18)) fifo_short - (.clk(sram_clk), .reset(reset), .clear(clear), - .datain(f18_in), .src_rdy_i(src_rdy_f18i), .dst_rdy_o(dst_rdy_f18i), .space(), - .dataout(f18_int), .src_rdy_o(src_rdy_f18int), .dst_rdy_i(dst_rdy_f18int), .occupied(f1_occ[4:0]) ); - - assign f1_occ[15:5] = 0; - - fifo_extram fifo_extram - (.reset(reset), .clear(clear), - .datain(f18_int), .src_rdy_i(src_rdy_f18int), .dst_rdy_o(dst_rdy_f18int), .space(), .occ_in(f1_occ), - .dataout(f18_out), .src_rdy_o(src_rdy_f18o), .dst_rdy_i(dst_rdy_f18o), .occupied(), .space_in(7), - .sram_clk(sram_clk), .sram_a(sram_a), .sram_d(sram_d), .sram_we(sram_we), - .sram_bw(sram_bw), .sram_adv(sram_adv), .sram_ce(sram_ce), .sram_oe(sram_oe), - .sram_mode(sram_mode), .sram_zz(sram_zz)); - -`define idt 1 -`ifdef idt - wire [15:0] dummy16; - wire [1:0] dummy2; - - idt71v65603s150 - ram_model(.A(sram_a[17:0]), - .adv_ld_(sram_adv), // advance (high) / load (low) - .bw1_(0), .bw2_(0), .bw3_(0), .bw4_(0), // byte write enables (low) - .ce1_(0), .ce2(1), .ce2_(0), // chip enables - .cen_(sram_ce), // clock enable (low) - .clk(sram_clk), // clock - .IO({dummy16,sram_d[15:0]}), - .IOP({dummy2,sram_d[17:16]}), // data bus - .lbo_(sram_mode), // linear burst order (low) - .oe_(sram_oe), // output enable (low) - .r_w_(sram_we)); // read (high) / write (low) -`else - cy1356 ram_model(.d(sram_d),.clk(sram_clk),.a(sram_a), - .bws(2'b00),.we_b(sram_we),.adv_lb(sram_adv), - .ce1b(0),.ce2(1),.ce3b(0), - .oeb(sram_oe),.cenb(sram_ce),.mode(sram_mode) ); -`endif // !`ifdef idt - - always @(posedge sram_clk) - if(dst_rdy_f18o & src_rdy_f18o) - $display("Read: %h",f18_out); - - always @(posedge sram_clk) - if(dst_rdy_f18int & src_rdy_f18int) - $display("Write: %h",f18_int); - - initial $dumpfile("fifo_extram_tb.vcd"); - initial $dumpvars(0,fifo_extram_tb); - - task SendPkt; - input [15:0] data_start; - input [31:0] data_len; - begin - @(posedge sram_clk); - f18_data = data_start; - f18_sof = 1; - f18_eof = 0; - src_rdy_f18i = 1; - while(~dst_rdy_f18i) - #1; - @(posedge sram_clk); - repeat(data_len - 2) - begin - f18_data = f18_data + 16'h0101; - f18_sof = 0; - while(~dst_rdy_f18i) - @(posedge sram_clk); - - @(posedge sram_clk); - end - f18_data = f18_data + 16'h0101; - f18_eof = 1; - while(~dst_rdy_f18i) - #1; - @(posedge sram_clk); - src_rdy_f18i = 0; - f18_data = 0; - f18_eof = 0; - end - endtask // SendPkt - - initial - begin - @(negedge reset); - @(posedge sram_clk); - @(posedge sram_clk); - #10000; - @(posedge sram_clk); - SendPkt(16'hA0B0, 100); - #10000; - //SendPkt(16'hC0D0, 220); - end - - initial - begin - #20000; - dst_rdy_f18o = 1; - end - - initial #200000 $finish; -endmodule // fifo_extram_tb - diff --git a/usrp2/fifo/buffer_int2.v b/usrp2/fifo/buffer_int2.v index 765b125fb..c73456b74 100644 --- a/usrp2/fifo/buffer_int2.v +++ b/usrp2/fifo/buffer_int2.v @@ -32,12 +32,13 @@ module buffer_int2 ); reg [BUF_SIZE-1:0] rd_addr, wr_addr; + wire [BUF_SIZE-1:0] rd_addr_next = rd_addr + 1; wire [31:0] ctrl; wire wr_done, wr_error, wr_idle; wire rd_done, rd_error, rd_idle; wire we, en, go; - reg [BUF_SIZE-1:0] lastline; + reg [BUF_SIZE-1:0] rd_length; wire read = ctrl[3]; wire rd_clear = ctrl[2]; wire write = ctrl[1]; @@ -72,13 +73,13 @@ module buffer_int2 begin rd_addr <= 0; rd_state <= PRE_READ; - lastline <= ctrl[15+BUF_SIZE:16]; + rd_length <= ctrl[15+BUF_SIZE:16]; end PRE_READ : begin rd_state <= READING; - rd_addr <= rd_addr + 1; + rd_addr <= rd_addr_next; rd_occ <= 2'b00; rd_sop <= 1; rd_eop <= 0; @@ -88,8 +89,8 @@ module buffer_int2 if(rd_ready_i) begin rd_sop <= 0; - rd_addr <= rd_addr + 1; - if(rd_addr == lastline) + rd_addr <= rd_addr_next; + if(rd_addr_next == rd_length) begin rd_eop <= 1; // FIXME assign occ here diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v index 34a05d91e..f7d7fb68e 100644 --- a/usrp2/fifo/dsp_framer36.v +++ b/usrp2/fifo/dsp_framer36.v @@ -2,7 +2,7 @@ // Frame DSP packets with a header line to be handled by the protocol machine module dsp_framer36 - #(parameter BUF_SIZE = 9) + #(parameter BUF_SIZE = 9, parameter PORT_SEL = 0) ( input clk, input rst, input clr, input [35:0] inp_data, input inp_valid, output inp_ready, @@ -29,8 +29,9 @@ module dsp_framer36 //The header is generated here from the count. wire [31:0] dsp_frm_data_bram; wire [15:0] dsp_frm_bytes = {dsp_frm_count, 2'b00}; + wire [1:0] port_sel_bits = PORT_SEL; assign out_data = - (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 16'b1, dsp_frm_bytes} : ( + (dsp_frm_state == DSP_FRM_STATE_WRITE_HDR)? {4'b0001, 13'b0, port_sel_bits, 1'b1, dsp_frm_bytes} : ( (dsp_frm_addr == dsp_frm_count) ? {4'b0010, dsp_frm_data_bram} : ( {4'b0000, dsp_frm_data_bram})); assign out_valid = ( diff --git a/usrp2/fifo/fifo18_to_fifo36.v b/usrp2/fifo/fifo18_to_fifo36.v deleted file mode 100644 index 25bb215a1..000000000 --- a/usrp2/fifo/fifo18_to_fifo36.v +++ /dev/null @@ -1,20 +0,0 @@ - -// For now just assume FIFO18 is same as FIFO19 without occupancy bit - -module fifo18_to_fifo36 - (input clk, input reset, input clear, - input [17:0] f18_datain, - input f18_src_rdy_i, - output f18_dst_rdy_o, - - output [35:0] f36_dataout, - output f36_src_rdy_o, - input f36_dst_rdy_i - ); - - fifo19_to_fifo36 fifo19_to_fifo36 - (.clk(clk), .reset(reset), .clear(clear), - .f19_datain({1'b0,f18_datain}), .f19_src_rdy_i(f18_src_rdy_i), .f19_dst_rdy_o(f18_dst_rdy_o), - .f36_dataout(f36_dataout), .f36_src_rdy_o(f36_src_rdy_o), .f36_dst_rdy_i(f36_dst_rdy_i) ); - -endmodule // fifo18_to_fifo36 diff --git a/usrp2/fifo/fifo19_to_fifo36.v b/usrp2/fifo/fifo19_to_fifo36.v index ae2edddc7..502821435 100644 --- a/usrp2/fifo/fifo19_to_fifo36.v +++ b/usrp2/fifo/fifo19_to_fifo36.v @@ -15,60 +15,73 @@ module fifo19_to_fifo36 input f36_dst_rdy_i, output [31:0] debug ); - - reg f36_sof, f36_eof; - reg [1:0] f36_occ; + // Shortfifo on input to guarantee no deadlock + wire [18:0] f19_data_int; + wire f19_src_rdy_int, f19_dst_rdy_int; + + fifo_short #(.WIDTH(19)) head_fifo + (.clk(clk),.reset(reset),.clear(clear), + .datain(f19_datain), .src_rdy_i(f19_src_rdy_i), .dst_rdy_o(f19_dst_rdy_o), + .dataout(f19_data_int), .src_rdy_o(f19_src_rdy_int), .dst_rdy_i(f19_dst_rdy_int), + .space(),.occupied() ); + + // Actual f19 to f36 which could deadlock if not connected to shortfifos + reg f36_sof_int, f36_eof_int; + reg [1:0] f36_occ_int; + wire [35:0] f36_data_int; + wire f36_src_rdy_int, f36_dst_rdy_int; + reg [1:0] state; reg [15:0] dat0, dat1; - wire f19_sof = f19_datain[16]; - wire f19_eof = f19_datain[17]; - wire f19_occ = f19_datain[18]; + wire f19_sof_int = f19_data_int[16]; + wire f19_eof_int = f19_data_int[17]; + wire f19_occ_int = f19_data_int[18]; - wire xfer_out = f36_src_rdy_o & f36_dst_rdy_i; + wire xfer_out = f36_src_rdy_int & f36_dst_rdy_int; always @(posedge clk) - if(f19_src_rdy_i & ((state==0)|xfer_out)) - f36_sof <= f19_sof; + if(f19_src_rdy_int & ((state==0)|xfer_out)) + f36_sof_int <= f19_sof_int; always @(posedge clk) - if(f19_src_rdy_i & ((state != 2)|xfer_out)) - f36_eof <= f19_eof; + if(f19_src_rdy_int & ((state != 2)|xfer_out)) + f36_eof_int <= f19_eof_int; always @(posedge clk) if(reset) begin state <= 0; - f36_occ <= 0; + f36_occ_int <= 0; end else - if(f19_src_rdy_i) + if(f19_src_rdy_int) case(state) 0 : begin - dat0 <= f19_datain; - if(f19_eof) + dat0 <= f19_data_int; + if(f19_eof_int) begin state <= 2; - f36_occ <= f19_occ ? 2'b01 : 2'b10; + f36_occ_int <= f19_occ_int ? 2'b01 : 2'b10; end else state <= 1; end 1 : begin - dat1 <= f19_datain; + dat1 <= f19_data_int; state <= 2; - if(f19_eof) - f36_occ <= f19_occ ? 2'b11 : 2'b00; + if(f19_eof_int) + f36_occ_int <= f19_occ_int ? 2'b11 : 2'b00; end 2 : if(xfer_out) begin - dat0 <= f19_datain; - if(f19_eof) // remain in state 2 if we are at eof - f36_occ <= f19_occ ? 2'b01 : 2'b10; + dat0 <= f19_data_int; + if(f19_eof_int) // remain in state 2 if we are at eof + f36_occ_int <= f19_occ_int ? 2'b01 : 2'b10; else state <= 1; end @@ -77,14 +90,21 @@ module fifo19_to_fifo36 if(xfer_out) begin state <= 0; - f36_occ <= 0; + f36_occ_int <= 0; end - assign f19_dst_rdy_o = xfer_out | (state != 2); - assign f36_dataout = LE ? {f36_occ,f36_eof,f36_sof,dat1,dat0} : - {f36_occ,f36_eof,f36_sof,dat0,dat1}; - assign f36_src_rdy_o = (state == 2); + assign f19_dst_rdy_int = xfer_out | (state != 2); + assign f36_data_int = LE ? {f36_occ_int,f36_eof_int,f36_sof_int,dat1,dat0} : + {f36_occ_int,f36_eof_int,f36_sof_int,dat0,dat1}; + assign f36_src_rdy_int = (state == 2); assign debug = state; + + // Shortfifo on output to guarantee no deadlock + fifo_short #(.WIDTH(36)) tail_fifo + (.clk(clk),.reset(reset),.clear(clear), + .datain(f36_data_int), .src_rdy_i(f36_src_rdy_int), .dst_rdy_o(f36_dst_rdy_int), + .dataout(f36_dataout), .src_rdy_o(f36_src_rdy_o), .dst_rdy_i(f36_dst_rdy_i), + .space(),.occupied() ); endmodule // fifo19_to_fifo36 diff --git a/usrp2/fifo/fifo36_to_fifo19.v b/usrp2/fifo/fifo36_to_fifo19.v index e016fe2c6..0e9b2d442 100644 --- a/usrp2/fifo/fifo36_to_fifo19.v +++ b/usrp2/fifo/fifo36_to_fifo19.v @@ -13,25 +13,37 @@ module fifo36_to_fifo19 output [18:0] f19_dataout, output f19_src_rdy_o, input f19_dst_rdy_i ); - - wire f36_sof = f36_datain[32]; - wire f36_eof = f36_datain[33]; - wire [1:0] f36_occ = f36_datain[35:34]; + + wire [18:0] f19_data_int; + wire f19_src_rdy_int, f19_dst_rdy_int; + wire [35:0] f36_data_int; + wire f36_src_rdy_int, f36_dst_rdy_int; + + // Shortfifo on input to guarantee no deadlock + fifo_short #(.WIDTH(36)) head_fifo + (.clk(clk),.reset(reset),.clear(clear), + .datain(f36_datain), .src_rdy_i(f36_src_rdy_i), .dst_rdy_o(f36_dst_rdy_o), + .dataout(f36_data_int), .src_rdy_o(f36_src_rdy_int), .dst_rdy_i(f36_dst_rdy_int), + .space(),.occupied() ); + + // Main fifo36_to_fifo19, needs shortfifos to guarantee no deadlock + wire [1:0] f36_occ_int = f36_data_int[35:34]; + wire f36_sof_int = f36_data_int[32]; + wire f36_eof_int = f36_data_int[33]; reg phase; + wire half_line = f36_eof_int & ((f36_occ_int==1)|(f36_occ_int==2)); - wire half_line = f36_eof & ((f36_occ==1)|(f36_occ==2)); - - assign f19_dataout[15:0] = (LE ^ phase) ? f36_datain[15:0] : f36_datain[31:16]; - assign f19_dataout[16] = phase ? 0 : f36_sof; - assign f19_dataout[17] = phase ? f36_eof : half_line; - assign f19_dataout[18] = f19_dataout[17] & ((f36_occ==1)|(f36_occ==3)); + assign f19_data_int[15:0] = (LE ^ phase) ? f36_data_int[15:0] : f36_data_int[31:16]; + assign f19_data_int[16] = phase ? 0 : f36_sof_int; + assign f19_data_int[17] = phase ? f36_eof_int : half_line; + assign f19_data_int[18] = f19_data_int[17] & ((f36_occ_int==1)|(f36_occ_int==3)); - assign f19_src_rdy_o = f36_src_rdy_i; - assign f36_dst_rdy_o = (phase | half_line) & f19_dst_rdy_i; + assign f19_src_rdy_int = f36_src_rdy_int; + assign f36_dst_rdy_int = (phase | half_line) & f19_dst_rdy_int; - wire f19_xfer = f19_src_rdy_o & f19_dst_rdy_i; - wire f36_xfer = f36_src_rdy_i & f36_dst_rdy_o; + wire f19_xfer = f19_src_rdy_int & f19_dst_rdy_int; + wire f36_xfer = f36_src_rdy_int & f36_dst_rdy_int; always @(posedge clk) if(reset) @@ -41,5 +53,11 @@ module fifo36_to_fifo19 else if(f19_xfer) phase <= 1; - + // Shortfifo on output to guarantee no deadlock + fifo_short #(.WIDTH(19)) tail_fifo + (.clk(clk),.reset(reset),.clear(clear), + .datain(f19_data_int), .src_rdy_i(f19_src_rdy_int), .dst_rdy_o(f19_dst_rdy_int), + .dataout(f19_dataout), .src_rdy_o(f19_src_rdy_o), .dst_rdy_i(f19_dst_rdy_i), + .space(),.occupied() ); + endmodule // fifo36_to_fifo19 diff --git a/usrp2/fifo/fifo36_to_ll8.v b/usrp2/fifo/fifo36_to_ll8.v index 9604d0e38..f1f0032e4 100644 --- a/usrp2/fifo/fifo36_to_ll8.v +++ b/usrp2/fifo/fifo36_to_ll8.v @@ -5,24 +5,31 @@ module fifo36_to_ll8 input f36_src_rdy_i, output f36_dst_rdy_o, - output reg [7:0] ll_data, - output ll_sof_n, - output ll_eof_n, - output ll_src_rdy_n, - input ll_dst_rdy_n, + output [7:0] ll_data, + output ll_sof, + output ll_eof, + output ll_src_rdy, + input ll_dst_rdy, output [31:0] debug); - wire ll_sof, ll_eof, ll_src_rdy; - assign ll_sof_n = ~ll_sof; - assign ll_eof_n = ~ll_eof; - assign ll_src_rdy_n = ~ll_src_rdy; - wire ll_dst_rdy = ~ll_dst_rdy_n; + // Shortfifo on input to guarantee no deadlock + wire [35:0] f36_data_int; + wire f36_src_rdy_int, f36_dst_rdy_int; + reg [7:0] ll_data_int; + wire ll_sof_int, ll_eof_int, ll_src_rdy_int, ll_dst_rdy_int; + + fifo_short #(.WIDTH(36)) head_fifo + (.clk(clk),.reset(reset),.clear(clear), + .datain(f36_data), .src_rdy_i(f36_src_rdy_i), .dst_rdy_o(f36_dst_rdy_o), + .dataout(f36_data_int), .src_rdy_o(f36_src_rdy_int), .dst_rdy_i(f36_dst_rdy_int), + .space(),.occupied() ); - wire f36_sof = f36_data[32]; - wire f36_eof = f36_data[33]; - wire f36_occ = f36_data[35:34]; - wire advance, end_early; + // Actual fifo36 to ll8, can deadlock if not connected to shortfifo + wire f36_sof_int = f36_data_int[32]; + wire f36_eof_int = f36_data_int[33]; + wire f36_occ_int = f36_data_int[35:34]; + wire advance, end_early; reg [1:0] state; assign debug = {29'b0,state}; @@ -31,29 +38,37 @@ module fifo36_to_ll8 state <= 0; else if(advance) - if(ll_eof) + if(ll_eof_int) state <= 0; else state <= state + 1; always @* case(state) - 0 : ll_data = f36_data[31:24]; - 1 : ll_data = f36_data[23:16]; - 2 : ll_data = f36_data[15:8]; - 3 : ll_data = f36_data[7:0]; - default : ll_data = f36_data[31:24]; + 0 : ll_data_int = f36_data_int[31:24]; + 1 : ll_data_int = f36_data_int[23:16]; + 2 : ll_data_int = f36_data_int[15:8]; + 3 : ll_data_int = f36_data_int[7:0]; + default : ll_data_int = f36_data_int[31:24]; endcase // case (state) - assign ll_sof = (state==0) & f36_sof; - assign ll_eof = f36_eof & (((state==0)&(f36_occ==1)) | - ((state==1)&(f36_occ==2)) | - ((state==2)&(f36_occ==3)) | + assign ll_sof_int = (state==0) & f36_sof_int; + assign ll_eof_int = f36_eof_int & (((state==0)&(f36_occ_int==1)) | + ((state==1)&(f36_occ_int==2)) | + ((state==2)&(f36_occ_int==3)) | (state==3)); - assign ll_src_rdy = f36_src_rdy_i; - - assign advance = ll_src_rdy & ll_dst_rdy; - assign f36_dst_rdy_o = advance & ((state==3)|ll_eof); + assign ll_src_rdy_int = f36_src_rdy_int; -endmodule // ll8_to_fifo36 + assign advance = ll_src_rdy_int & ll_dst_rdy_int; + assign f36_dst_rdy_int= advance & ((state==3)|ll_eof_int); + + // Short FIFO on output to guarantee no deadlock + ll8_shortfifo tail_fifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(ll_data_int), .sof_i(ll_sof_int), .eof_i(ll_eof_int), + .error_i(0), .src_rdy_i(ll_src_rdy_int), .dst_rdy_o(ll_dst_rdy_int), + .dataout(ll_data), .sof_o(ll_sof), .eof_o(ll_eof), + .error_o(), .src_rdy_o(ll_src_rdy), .dst_rdy_i(ll_dst_rdy)); + +endmodule // fifo36_to_ll8 diff --git a/usrp2/fifo/ll8_to_fifo19.v b/usrp2/fifo/ll8_to_fifo19.v index af3b91afb..ac8ac19a6 100644 --- a/usrp2/fifo/ll8_to_fifo19.v +++ b/usrp2/fifo/ll8_to_fifo19.v @@ -2,41 +2,47 @@ module ll8_to_fifo19 (input clk, input reset, input clear, input [7:0] ll_data, - input ll_sof_n, - input ll_eof_n, - input ll_src_rdy_n, - output ll_dst_rdy_n, + input ll_sof, + input ll_eof, + input ll_src_rdy, + output ll_dst_rdy, output [18:0] f19_data, output f19_src_rdy_o, input f19_dst_rdy_i ); + + // Short FIFO on input to guarantee no deadlock + wire [7:0] ll_data_int; + wire ll_sof_int, ll_eof_int, ll_src_rdy_int, ll_dst_rdy_int; + ll8_shortfifo head_fifo + (.clk(clk), .reset(reset), .clear(clear), + .datain(ll_data), .sof_i(ll_sof), .eof_i(ll_eof), + .error_i(0), .src_rdy_i(ll_src_rdy), .dst_rdy_o(ll_dst_rdy), + .dataout(ll_data_int), .sof_o(ll_sof_int), .eof_o(ll_eof_int), + .error_o(), .src_rdy_o(ll_src_rdy_int), .dst_rdy_i(ll_dst_rdy_int)); + + // Actual ll8_to_fifo19 which could deadlock if not connected to a shortfifo localparam XFER_EMPTY = 0; localparam XFER_HALF = 1; localparam XFER_HALF_WRITE = 3; - // Why anybody would use active low in an FPGA is beyond me... - wire ll_sof = ~ll_sof_n; - wire ll_eof = ~ll_eof_n; - wire ll_src_rdy = ~ll_src_rdy_n; - wire ll_dst_rdy; - assign ll_dst_rdy_n = ~ll_dst_rdy; - - wire xfer_out = f19_src_rdy_o & f19_dst_rdy_i; - wire xfer_in = ll_src_rdy & ll_dst_rdy; - - reg hold_sof; - wire f19_sof, f19_eof, f19_occ; + wire [18:0] f19_data_int; + wire f19_sof_int, f19_eof_int, f19_occ_int, f19_src_rdy_int, f19_dst_rdy_int; + + wire xfer_out = f19_src_rdy_int & f19_dst_rdy_int; + wire xfer_in = ll_src_rdy_int & ll_dst_rdy_int; + reg hold_sof; - reg [1:0] state; - reg [7:0] hold_reg; + reg [1:0] state; + reg [7:0] hold_reg; always @(posedge clk) - if(ll_src_rdy & (state==XFER_EMPTY)) - hold_reg <= ll_data; + if(ll_src_rdy_int & (state==XFER_EMPTY)) + hold_reg <= ll_data_int; always @(posedge clk) - if(ll_sof & (state==XFER_EMPTY)) + if(ll_sof_int & (state==XFER_EMPTY)) hold_sof <= 1; else if(xfer_out) hold_sof <= 0; @@ -47,27 +53,35 @@ module ll8_to_fifo19 else case(state) XFER_EMPTY : - if(ll_src_rdy) - if(ll_eof) + if(ll_src_rdy_int) + if(ll_eof_int) state <= XFER_HALF_WRITE; else state <= XFER_HALF; XFER_HALF : - if(ll_src_rdy & f19_dst_rdy_i) + if(ll_src_rdy_int & f19_dst_rdy_int) state <= XFER_EMPTY; XFER_HALF_WRITE : - if(f19_dst_rdy_i) + if(f19_dst_rdy_int) state <= XFER_EMPTY; endcase // case (state) - assign ll_dst_rdy = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_i); - assign f19_src_rdy_o = (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy); + assign ll_dst_rdy_int = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_int); + assign f19_src_rdy_int= (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy_int); - assign f19_sof = hold_sof | (ll_sof & (state==XFER_HALF)); - assign f19_eof = (state == XFER_HALF_WRITE) | ll_eof; - assign f19_occ = (state == XFER_HALF_WRITE); + assign f19_sof_int = hold_sof | (ll_sof_int & (state==XFER_HALF)); + assign f19_eof_int = (state == XFER_HALF_WRITE) | ll_eof_int; + assign f19_occ_int = (state == XFER_HALF_WRITE); - assign f19_data = {f19_occ,f19_eof,f19_sof,hold_reg,ll_data}; + assign f19_data_int = {f19_occ_int,f19_eof_int,f19_sof_int,hold_reg,ll_data_int}; + + // Shortfifo on output to guarantee no deadlock + fifo_short #(.WIDTH(19)) tail_fifo + (.clk(clk),.reset(reset),.clear(clear), + .datain(f19_data_int), .src_rdy_i(f19_src_rdy_int), .dst_rdy_o(f19_dst_rdy_int), + .dataout(f19_data), .src_rdy_o(f19_src_rdy_o), .dst_rdy_i(f19_dst_rdy_i), + .space(),.occupied() ); + endmodule // ll8_to_fifo19 diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v index 161b59016..61f90d3cf 100644 --- a/usrp2/fifo/packet_router.v +++ b/usrp2/fifo/packet_router.v @@ -33,7 +33,8 @@ module packet_router // Input Interfaces (in to router) input [35:0] ser_inp_data, input ser_inp_valid, output ser_inp_ready, - input [35:0] dsp_inp_data, input dsp_inp_valid, output dsp_inp_ready, + input [35:0] dsp0_inp_data, input dsp0_inp_valid, output dsp0_inp_ready, + input [35:0] dsp1_inp_data, input dsp1_inp_valid, output dsp1_inp_ready, input [35:0] eth_inp_data, input eth_inp_valid, output eth_inp_ready, input [35:0] err_inp_data, input err_inp_valid, output err_inp_ready, @@ -83,11 +84,11 @@ module packet_router ); //setting register to program the UDP data ports - wire [15:0] dsp0_udp_port, dsp1_udp_port; - setting_reg #(.my_addr(CTRL_BASE+2)) sreg_data_ports( + wire [15:0] dsp_udp_port; + setting_reg #(.my_addr(CTRL_BASE+2), .width(16)) sreg_data_ports( .clk(stream_clk),.rst(stream_rst), .strobe(set_stb),.addr(set_addr),.in(set_data), - .out({dsp1_udp_port, dsp0_udp_port}),.changed() + .out(dsp_udp_port),.changed() ); //assign status output signals @@ -116,6 +117,11 @@ module packet_router wire _eth_inp_valid; wire _eth_inp_ready; + // dummy signals to connect fifo_short + wire [35:0] _com_inp_data; + wire _com_inp_valid; + wire _com_inp_ready; + valve36 eth_inp_valve ( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .shutoff(~master_mode_flag), .data_i(eth_inp_data), .src_rdy_i(eth_inp_valid), .dst_rdy_o(eth_inp_ready), @@ -126,10 +132,17 @@ module packet_router .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .cross(~master_mode_flag), .data0_i(_eth_inp_data), .src0_rdy_i(_eth_inp_valid), .dst0_rdy_o(_eth_inp_ready), .data1_i(ser_inp_data), .src1_rdy_i(ser_inp_valid), .dst1_rdy_o(ser_inp_ready), - .data0_o(com_inp_data), .src0_rdy_o(com_inp_valid), .dst0_rdy_i(com_inp_ready), + .data0_o(_com_inp_data), .src0_rdy_o(_com_inp_valid), .dst0_rdy_i(_com_inp_ready), .data1_o(ext_inp_data), .src1_rdy_o(ext_inp_valid), .dst1_rdy_i(ext_inp_ready) ); + // short fifo in the packet inspection path to help timing + fifo_short #(.WIDTH(36)) com_inp_fifo + (.clk(stream_clk), .reset(stream_rst), .clear(stream_clr), + .datain(_com_inp_data), .src_rdy_i(_com_inp_valid), .dst_rdy_o(_com_inp_ready), + .dataout(com_inp_data), .src_rdy_o(com_inp_valid), .dst_rdy_i(com_inp_ready), + .space(), .occupied() ); + //////////////////////////////////////////////////////////////////// // Communication output sink crossbar // When in master mode: @@ -172,30 +185,33 @@ module packet_router //////////////////////////////////////////////////////////////////// //streaming signals from the dsp framer to the combiner - wire [35:0] dsp_frm_data; - wire dsp_frm_valid; - wire dsp_frm_ready; + wire [35:0] dsp0_frm_data, dsp1_frm_data; + wire dsp0_frm_valid, dsp1_frm_valid; + wire dsp0_frm_ready, dsp1_frm_ready; //dummy signals to join the the muxes below wire [35:0] _combiner0_data, _combiner1_data; wire _combiner0_valid, _combiner1_valid; wire _combiner0_ready, _combiner1_ready; - fifo36_mux _com_output_combiner0( + fifo36_mux #(.prio(0)) // No priority, fair sharing + _com_output_combiner0( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .data0_i(dsp_frm_data), .src0_rdy_i(dsp_frm_valid), .dst0_rdy_o(dsp_frm_ready), - .data1_i(err_inp_data), .src1_rdy_i(err_inp_valid), .dst1_rdy_o(err_inp_ready), + .data0_i(err_inp_data), .src0_rdy_i(err_inp_valid), .dst0_rdy_o(err_inp_ready), + .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready), .data_o(_combiner0_data), .src_rdy_o(_combiner0_valid), .dst_rdy_i(_combiner0_ready) ); - fifo36_mux _com_output_combiner1( + fifo36_mux #(.prio(0)) // No priority, fair sharing + _com_output_combiner1( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), - .data0_i(32'b0), .src0_rdy_i(1'b0), .dst0_rdy_o(), //mux out from dsp1 can go here - .data1_i(cpu_inp_data), .src1_rdy_i(cpu_inp_valid), .dst1_rdy_o(cpu_inp_ready), + .data0_i(dsp0_frm_data), .src0_rdy_i(dsp0_frm_valid), .dst0_rdy_o(dsp0_frm_ready), + .data1_i(dsp1_frm_data), .src1_rdy_i(dsp1_frm_valid), .dst1_rdy_o(dsp1_frm_ready), .data_o(_combiner1_data), .src_rdy_o(_combiner1_valid), .dst_rdy_i(_combiner1_ready) ); - fifo36_mux com_output_source( + fifo36_mux #(.prio(1)) // Give priority to err/cpu over dsp + com_output_source( .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .data0_i(_combiner0_data), .src0_rdy_i(_combiner0_valid), .dst0_rdy_o(_combiner0_ready), .data1_i(_combiner1_data), .src1_rdy_i(_combiner1_valid), .dst1_rdy_o(_combiner1_ready), @@ -364,7 +380,7 @@ module packet_router end //UDP data port and VRT: - else if ((com_insp_dregs_udp_dst_port == dsp0_udp_port) && (com_insp_dregs_vrt_size != 16'h0)) begin + else if ((com_insp_dregs_udp_dst_port == dsp_udp_port) && (com_insp_dregs_vrt_size != 16'h0)) begin com_insp_dest <= COM_INSP_DEST_DSP; com_insp_dreg_count <= COM_INSP_DREGS_DSP_OFFSET; end @@ -448,11 +464,16 @@ module packet_router //////////////////////////////////////////////////////////////////// // DSP input framer //////////////////////////////////////////////////////////////////// + dsp_framer36 #(.BUF_SIZE(BUF_SIZE), .PORT_SEL(0)) dsp0_framer36( + .clk(stream_clk), .rst(stream_rst), .clr(stream_clr), + .inp_data(dsp0_inp_data), .inp_valid(dsp0_inp_valid), .inp_ready(dsp0_inp_ready), + .out_data(dsp0_frm_data), .out_valid(dsp0_frm_valid), .out_ready(dsp0_frm_ready) + ); - dsp_framer36 #(.BUF_SIZE(BUF_SIZE)) dsp0_framer36( + dsp_framer36 #(.BUF_SIZE(BUF_SIZE), .PORT_SEL(2)) dsp1_framer36( .clk(stream_clk), .rst(stream_rst), .clr(stream_clr), - .inp_data(dsp_inp_data), .inp_valid(dsp_inp_valid), .inp_ready(dsp_inp_ready), - .out_data(dsp_frm_data), .out_valid(dsp_frm_valid), .out_ready(dsp_frm_ready) + .inp_data(dsp1_inp_data), .inp_valid(dsp1_inp_valid), .inp_ready(dsp1_inp_ready), + .out_data(dsp1_frm_data), .out_valid(dsp1_frm_valid), .out_ready(dsp1_frm_ready) ); //////////////////////////////////////////////////////////////////// @@ -508,7 +529,7 @@ module packet_router assign debug = { //inputs to the router (8) - dsp_inp_ready, dsp_inp_valid, + dsp0_inp_ready, dsp0_inp_valid, ser_inp_ready, ser_inp_valid, eth_inp_ready, eth_inp_valid, cpu_inp_ready, cpu_inp_valid, diff --git a/usrp2/simple_gemac/simple_gemac_wrapper.v b/usrp2/simple_gemac/simple_gemac_wrapper.v index efcf89276..b783729d5 100644 --- a/usrp2/simple_gemac/simple_gemac_wrapper.v +++ b/usrp2/simple_gemac/simple_gemac_wrapper.v @@ -1,7 +1,7 @@ module simple_gemac_wrapper #(parameter RXFIFOSIZE=9, - parameter TXFIFOSIZE=6) + parameter TXFIFOSIZE=9) (input clk125, input reset, // GMII output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD, @@ -30,7 +30,9 @@ module simple_gemac_wrapper wire pause_req; wire pause_request_en, pause_respect_en; wire [15:0] pause_time, pause_thresh, pause_time_req, rx_fifo_space; - + + wire [31:0] debug_state; + wire tx_reset, rx_reset; reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset)); reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset)); @@ -49,7 +51,8 @@ module simple_gemac_wrapper .rx_clk(rx_clk), .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack), .tx_clk(tx_clk), .tx_data(tx_data), - .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack) + .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack), + .debug(debug_state) ); simple_gemac_wb simple_gemac_wb @@ -65,14 +68,12 @@ module simple_gemac_wrapper // RX FIFO Chain wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; + wire [7:0] rx_ll_data; - wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2; - wire rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n; - - wire [7:0] rx_ll_data, rx_ll_data2; - - wire [35:0] rx_f36_data_int1; - wire rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1; + wire [18:0] rx_f19_data_int1, rx_f19_data_int2; + wire rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_src_rdy_int2, rx_f19_dst_rdy_int2; + wire [35:0] rx_f36_data_int; + wire rx_f36_src_rdy_int, rx_f36_dst_rdy_int; rxmac_to_ll8 rx_adapt (.clk(rx_clk), .reset(rx_reset), .clear(0), @@ -80,86 +81,69 @@ module simple_gemac_wrapper .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(), // error also encoded in sof/eof .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy)); - ll8_shortfifo rx_sfifo + ll8_to_fifo19 ll8_to_fifo19 (.clk(rx_clk), .reset(rx_reset), .clear(0), - .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof), - .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), - .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2), - .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2)); + .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), + .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy), + .f19_data(rx_f19_data_int1), .f19_src_rdy_o(rx_f19_src_rdy_int1), .f19_dst_rdy_i(rx_f19_dst_rdy_int1)); - assign rx_ll_dst_rdy2 = ~rx_ll_dst_rdy2_n; - assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2; - assign rx_ll_sof2_n = ~rx_ll_sof2; - assign rx_ll_eof2_n = ~rx_ll_eof2; - - ll8_to_fifo36 ll8_to_fifo36 + fifo19_rxrealign fifo19_rxrealign + (.clk(rx_clk), .reset(rx_reset), .clear(0), + .datain(rx_f19_data_int1), .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1), + .dataout(rx_f19_data_int2), .src_rdy_o(rx_f19_src_rdy_int2), .dst_rdy_i(rx_f19_dst_rdy_int2) ); + + fifo19_to_fifo36 rx_fifo19_to_fifo36 (.clk(rx_clk), .reset(rx_reset), .clear(0), - .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n), - .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n), - .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1)); + .f19_datain(rx_f19_data_int2), .f19_src_rdy_i(rx_f19_src_rdy_int2), .f19_dst_rdy_o(rx_f19_dst_rdy_int2), + .f36_dataout(rx_f36_data_int), .f36_src_rdy_o(rx_f36_src_rdy_int), .f36_dst_rdy_i(rx_f36_dst_rdy_int) ); fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo - (.wclk(rx_clk), .datain(rx_f36_data_int1), - .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(rx_fifo_space), + (.wclk(rx_clk), .datain(rx_f36_data_int), + .src_rdy_i(rx_f36_src_rdy_int), .dst_rdy_o(rx_f36_dst_rdy_int), .space(rx_fifo_space), .rclk(sys_clk), .dataout(rx_f36_data), .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset)); // TX FIFO Chain wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy; - wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2; - wire tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n; - wire [7:0] tx_ll_data, tx_ll_data2; + wire [7:0] tx_ll_data; wire [35:0] tx_f36_data_int1; wire tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1; fifo_2clock_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo - (.wclk(sys_clk), .datain(tx_f36_data), - .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(), - .rclk(tx_clk), .dataout(tx_f36_data_int1), - .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), .arst(reset)); + (.wclk(sys_clk), .datain(tx_f36_data), .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(), + .rclk(tx_clk), .dataout(tx_f36_data_int1), .src_rdy_o(tx_f36_src_rdy_int1), .dst_rdy_i(tx_f36_dst_rdy_int1), .occupied(), + .arst(reset)); fifo36_to_ll8 fifo36_to_ll8 (.clk(tx_clk), .reset(tx_reset), .clear(clear), .f36_data(tx_f36_data_int1), .f36_src_rdy_i(tx_f36_src_rdy_int1), .f36_dst_rdy_o(tx_f36_dst_rdy_int1), - .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n), - .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n)); + .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), + .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy)); - assign tx_ll_sof2 = ~tx_ll_sof2_n; - assign tx_ll_eof2 = ~tx_ll_eof2_n; - assign tx_ll_src_rdy2 = ~tx_ll_src_rdy2_n; - assign tx_ll_dst_rdy2_n = ~tx_ll_dst_rdy2; - - ll8_shortfifo tx_sfifo - (.clk(tx_clk), .reset(tx_reset), .clear(clear), - .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2), - .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2), - .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof), - .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy)); - ll8_to_txmac ll8_to_txmac (.clk(tx_clk), .reset(tx_reset), .clear(clear), .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof), .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy), .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)); + // Flow Control flow_ctrl_rx flow_ctrl_rx (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh), .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space), .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req)); wire [31:0] debug_tx, debug_rx; - + assign debug_tx = { { tx_ll_data }, - { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, - tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 }, + { tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, 4'b0 }, { tx_valid, tx_error, tx_ack, tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1, tx_f36_data_int1[34:32]}, { tx_data} }; assign debug_rx = { { rx_ll_data }, - { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, - rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 }, - { rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1, rx_f36_data_int1[34:32]}, + { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 4'b0 }, + { rx_valid, rx_error, rx_ack, rx_f36_src_rdy_int, rx_f36_dst_rdy_int, rx_f36_data_int[34:32]}, { rx_data} }; assign debug = debug_rx; endmodule // simple_gemac_wrapper + diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19.v b/usrp2/simple_gemac/simple_gemac_wrapper19.v index 6cdbd1a59..c155b7d41 100644 --- a/usrp2/simple_gemac/simple_gemac_wrapper19.v +++ b/usrp2/simple_gemac/simple_gemac_wrapper19.v @@ -68,14 +68,10 @@ module simple_gemac_wrapper19 // RX FIFO Chain wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; + wire [7:0] rx_ll_data; - wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2; - wire rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n; - - wire [7:0] rx_ll_data, rx_ll_data2; - - wire [18:0] rx_f19_data_int1; - wire rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1; + wire [18:0] rx_f19_data_int1, rx_f19_data_int2; + wire rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_src_rdy_int2, rx_f19_dst_rdy_int2; rxmac_to_ll8 rx_adapt (.clk(rx_clk), .reset(rx_reset), .clear(0), @@ -83,28 +79,21 @@ module simple_gemac_wrapper19 .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(), // error also encoded in sof/eof .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy)); - ll8_shortfifo rx_sfifo - (.clk(rx_clk), .reset(rx_reset), .clear(0), - .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof), - .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), - .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2), - .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2)); - - assign rx_ll_dst_rdy2 = ~rx_ll_dst_rdy2_n; - assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2; - assign rx_ll_sof2_n = ~rx_ll_sof2; - assign rx_ll_eof2_n = ~rx_ll_eof2; - ll8_to_fifo19 ll8_to_fifo19 (.clk(rx_clk), .reset(rx_reset), .clear(0), - .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n), - .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n), + .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), + .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy), .f19_data(rx_f19_data_int1), .f19_src_rdy_o(rx_f19_src_rdy_int1), .f19_dst_rdy_i(rx_f19_dst_rdy_int1)); + fifo19_rxrealign fifo19_rxrealign + (.clk(rx_clk), .reset(rx_reset), .clear(0), + .datain(rx_f19_data_int1), .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1), + .dataout(rx_f19_data_int2), .src_rdy_o(rx_f19_src_rdy_int2), .dst_rdy_i(rx_f19_dst_rdy_int2) ); + //fifo_2clock_cascade #(.WIDTH(19), .SIZE(RXFIFOSIZE)) rx_2clk_fifo fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo - (.wclk(rx_clk), .datain(rx_f19_data_int1), - .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1), .space(rx_fifo_space), + (.wclk(rx_clk), .datain(rx_f19_data_int2), + .src_rdy_i(rx_f19_src_rdy_int2), .dst_rdy_o(rx_f19_dst_rdy_int2), .space(rx_fifo_space), .rclk(sys_clk), .dataout(rx_f19_data), .src_rdy_o(rx_f19_src_rdy), .dst_rdy_i(rx_f19_dst_rdy), .occupied(), .arst(reset)); @@ -160,8 +149,7 @@ module simple_gemac_wrapper19 { tx_valid, tx_error, tx_ack, tx_f19_src_rdy_int1, tx_f19_dst_rdy_int1, tx_f19_data_int1[18:16]}, { tx_data} }; assign debug_rx = { { rx_f19_src_rdy, rx_f19_dst_rdy, debug_state[5:0] }, - { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, - rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 }, + { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 4'b0 }, { rx_valid, rx_error, rx_ack, rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_data_int1[18:16]}, { rx_data} }; diff --git a/usrp2/top/safe_u2plus/Makefile b/usrp2/top/safe_u2plus/Makefile index 62a02ff40..b72241050 100644 --- a/usrp2/top/safe_u2plus/Makefile +++ b/usrp2/top/safe_u2plus/Makefile @@ -117,7 +117,6 @@ coregen/fifo_xlnx_512x36_2clk.v \ coregen/fifo_xlnx_512x36_2clk.xco \ coregen/fifo_xlnx_64x36_2clk.v \ coregen/fifo_xlnx_64x36_2clk.xco \ -extram/wb_zbt16_b.v \ opencores/8b10b/decode_8b10b.v \ opencores/8b10b/encode_8b10b.v \ opencores/aemb/rtl/verilog/aeMB_bpcu.v \ diff --git a/usrp2/top/u1e_passthru/Makefile b/usrp2/top/u1e_passthru/Makefile index d1950629b..f2d835608 100644 --- a/usrp2/top/u1e_passthru/Makefile +++ b/usrp2/top/u1e_passthru/Makefile @@ -23,7 +23,6 @@ include ../../opencores/Makefile.srcs include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs -include ../../extram/Makefile.srcs include ../../gpmc/Makefile.srcs ################################################## @@ -51,7 +50,7 @@ passthru.ucf SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ $(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \ $(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \ -$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \ +$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) \ $(GPMC_SRCS) ################################################## diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile index 05ada2476..e9b43491a 100644 --- a/usrp2/top/u2_rev3/Makefile +++ b/usrp2/top/u2_rev3/Makefile @@ -23,7 +23,6 @@ include ../../opencores/Makefile.srcs include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs -include ../../extram/Makefile.srcs include ../../extramfifo/Makefile.srcs diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index ab2ed49f0..7504efeb3 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -3,7 +3,6 @@ // //////////////////////////////////////////////////////////////////////////////// module u2_core - #(parameter RAM_SIZE=16384, parameter RAM_AW=14) (// Clocks input dsp_clk, input wb_clk, @@ -137,20 +136,24 @@ module u2_core input [3:0] clock_divider ); - localparam SR_BUF_POOL = 64; // Uses 1 reg + localparam SR_MISC = 0; // Uses 9 regs + localparam SR_BUF_POOL = 64; // Uses 4 regs localparam SR_UDP_SM = 96; // 64 regs - localparam SR_RX_DSP = 160; // 16 - localparam SR_RX_CTRL = 176; // 16 + localparam SR_RX_DSP0 = 160; // 16 + localparam SR_RX_CTRL0 = 176; // 16 localparam SR_TIME64 = 192; // 3 localparam SR_SIMTIMER = 198; // 2 localparam SR_TX_DSP = 208; // 16 localparam SR_TX_CTRL = 224; // 16 - + localparam SR_RX_DSP1 = 240; + localparam SR_RX_CTRL1 = 32; + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs - localparam DSP_TX_FIFOSIZE = 10; - localparam DSP_RX_FIFOSIZE = 10; - localparam ETH_TX_FIFOSIZE = 10; + // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo + localparam DSP_RX_FIFOSIZE = 9; + localparam ETH_TX_FIFOSIZE = 9; localparam ETH_RX_FIFOSIZE = 11; localparam SERDES_TX_FIFOSIZE = 9; localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? @@ -159,13 +162,14 @@ module u2_core wire [31:0] set_data, set_data_dsp; wire set_stb, set_stb_dsp; - wire ram_loader_done; - wire ram_loader_rst, wb_rst, dsp_rst; - assign dsp_rst = wb_rst; - + wire ram_loader_done, ram_loader_rst; + wire wb_rst; + wire dsp_rst = wb_rst; + wire [31:0] status; wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; - wire proc_int, overrun, underrun, uart_tx_int, uart_rx_int; + wire proc_int, overrun0, overrun1, underrun; + wire uart_tx_int, uart_rx_int; wire [31:0] debug_gpio_0, debug_gpio_1; wire [31:0] atr_lines; @@ -182,10 +186,8 @@ module u2_core wire [31:0] irq; wire [63:0] vita_time, vita_time_pps; - wire run_rx, run_tx; - reg run_rx_d1; - always @(posedge dsp_clk) - run_rx_d1 <= run_rx; + wire run_rx0, run_rx1, run_tx; + reg run_rx0_d1, run_rx1_d1; // /////////////////////////////////////////////////////////////////////////////////////////////// // Wishbone Single Master INTERCON @@ -291,7 +293,7 @@ module u2_core wire [15:0] ram_loader_adr; wire [3:0] ram_loader_sel; wire ram_loader_stb, ram_loader_we; - ram_loader #(.AWIDTH(aw),.RAM_SIZE(RAM_SIZE)) + ram_loader #(.AWIDTH(aw),.RAM_SIZE(16384)) ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst), .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr), .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel), @@ -324,21 +326,21 @@ module u2_core // I-port connects directly to processor and ram loader wire flush_icache; - ram_harvard #(.AWIDTH(RAM_AW),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6)) + ram_harvard #(.AWIDTH(14),.RAM_SIZE(16384),.ICWIDTH(7),.DCWIDTH(6)) sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst), - .ram_loader_adr_i(ram_loader_adr[RAM_AW-1:0]), .ram_loader_dat_i(ram_loader_dat), + .ram_loader_adr_i(ram_loader_adr[13:0]), .ram_loader_dat_i(ram_loader_dat), .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel), .ram_loader_we_i(ram_loader_we), .ram_loader_done_i(ram_loader_done), .if_adr(16'b0), .if_data(), - .dwb_adr_i(s0_adr[RAM_AW-1:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), + .dwb_adr_i(s0_adr[13:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i), .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel), .flush_icache(flush_icache)); - setting_reg #(.my_addr(7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(SR_MISC+7)) sr_icache (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(flush_icache)); // ///////////////////////////////////////////////////////////////////////// @@ -347,15 +349,13 @@ module u2_core wire rd1_ready_i, rd1_ready_o; wire rd2_ready_i, rd2_ready_o; wire rd3_ready_i, rd3_ready_o; - wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + wire [35:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; wire wr0_ready_i, wr0_ready_o; wire wr1_ready_i, wr1_ready_o; wire wr2_ready_i, wr2_ready_o; wire wr3_ready_i, wr3_ready_o; - wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + wire [35:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; wire [35:0] tx_err_data; wire tx_err_src_rdy, tx_err_dst_rdy; @@ -373,14 +373,15 @@ module u2_core .status(status), .sys_int_o(buffer_int), .debug(router_debug), - .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), - .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), - .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o), + .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o), + .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), - .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), - .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), - .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) + .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), + .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) ); // ///////////////////////////////////////////////////////////////////////// @@ -416,7 +417,7 @@ module u2_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd4; + localparam compat_num = 32'd5; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), @@ -432,56 +433,21 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // Ethernet MAC Slave #6 - wire [18:0] rx_f19_data, tx_f19_data; - wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy; - - simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 + simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), + .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper19 (.clk125(clk_to_mac), .reset(wb_rst), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), .sys_clk(dsp_clk), - .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), - .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), + .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), + .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), .mdio(MDIO), .mdc(MDC), .debug(debug_mac)); - wire [35:0] rx_f36_data, tx_f36_data; - wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; - - wire [18:0] _rx_f19_data; - wire _rx_f19_src_rdy, _rx_f19_dst_rdy; - - //mac rx to eth input... - fifo19_rxrealign fifo19_rxrealign - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy), - .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) ); - - fifo19_to_fifo36 eth_inp_fifo19_to_fifo36 - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy), - .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) ); - - fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy), - .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); - - //eth output to mac tx... - fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy)); - - fifo36_to_fifo19 eth_out_fifo36_to_fifo19 - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), - .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) ); - // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #7 settings_bus settings_bus @@ -504,13 +470,13 @@ module u2_core wire phy_reset; assign PHY_RESETn = ~phy_reset; - setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + setting_reg #(.my_addr(SR_MISC+0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), .in(set_data),.out(clock_outs),.changed()); - setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(SR_MISC+1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(serdes_outs),.changed()); - setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(SR_MISC+2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(adc_outs),.changed()); - setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phy_reset),.changed()); // ///////////////////////////////////////////////////////////////////////// @@ -520,12 +486,12 @@ module u2_core // In Rev3 there are only 6 leds, and the highest one is on the ETH connector wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {run_tx, run_rx, clk_status, serdes_link_up, 1'b0}; + wire [7:0] led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up, 1'b0}; - setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(8),.width(8), .at_reset(8'b0001_1110)) + setting_reg #(.my_addr(SR_MISC+8),.width(8), .at_reset(8'b0001_1110)) sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); assign leds = (led_src & led_hw) | (~led_src & led_sw); @@ -537,7 +503,7 @@ module u2_core wire underrun_wb, overrun_wb, pps_wb; oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); - oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb)); + oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun0 | overrun1), .clk_out(wb_clk), .out(overrun_wb)); oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); assign irq= {{8'b0}, @@ -580,7 +546,7 @@ module u2_core (.clk_i(wb_clk),.rst_i(wb_rst), .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), - .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + .run_rx(run_rx0_d1 | run_rx1_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); // ////////////////////////////////////////////////////////////////////////// // Time Sync, Slave #12 @@ -601,50 +567,72 @@ module u2_core assign sd_dat_i[31:8] = 0; // ///////////////////////////////////////////////////////////////////////// - // DSP RX - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy; - wire [99:0] rx_data; - wire [35:0] rx1_data; + // DSP RX 0 + wire [31:0] sample_rx0; + wire [35:0] rx0_data; + wire clear_rx0, strobe_rx0, rx0_dst_rdy, rx0_src_rdy; + + always @(posedge dsp_clk) + run_rx0_d1 <= run_rx0; - dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); + .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), + .debug() ); - wire [31:0] vrc_debug; - wire clear_rx; - - setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear + setting_reg #(.my_addr(SR_RX_CTRL0+3)) sr_clear_rx0 (.clk(dsp_clk),.rst(dsp_rst), .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), - .out(),.changed(clear_rx)); + .out(),.changed(clear_rx0)); - vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + vita_rx_chain #(.BASE(SR_RX_CTRL0)) vita_rx_chain0 + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time), .overrun(overrun), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy), - .debug_rx(vrc_debug)); + .vita_time(vita_time), .overrun(overrun0), + .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), + .rx_data_o(rx0_data), .rx_src_rdy_o(rx0_src_rdy), .rx_dst_rdy_i(rx0_dst_rdy), + .debug() ); + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade0 + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0), + .datain(rx0_data), .src_rdy_i(rx0_src_rdy), .dst_rdy_o(rx0_dst_rdy), + .dataout(wr1_dat), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); - wire [3:0] vita_state; + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 1 + wire [31:0] sample_rx1; + wire [35:0] rx1_data; + wire clear_rx1, strobe_rx1, rx1_dst_rdy, rx1_src_rdy; + + always @(posedge dsp_clk) + run_rx1_d1 <= run_rx1; - vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), + .debug() ); + + setting_reg #(.my_addr(SR_RX_CTRL1+3)) sr_clear_rx1 + (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx1)); + + vita_rx_chain #(.BASE(SR_RX_CTRL1)) vita_rx_chain1 + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), - .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), - .fifo_occupied(), .fifo_full(), .fifo_empty(), - .debug_rx(vita_state) ); + .vita_time(vita_time), .overrun(overrun1), + .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), + .rx_data_o(rx1_data), .rx_src_rdy_o(rx1_src_rdy), .rx_dst_rdy_i(rx1_dst_rdy), + .debug() ); - fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade1 + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), - .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); + .dataout(wr3_dat), .src_rdy_o(wr3_ready_i), .dst_rdy_i(wr3_ready_o)); // /////////////////////////////////////////////////////////////////////////////////// // DSP TX @@ -672,10 +660,10 @@ module u2_core .RAM_LDn(RAM_LDn), .RAM_OEn(RAM_OEn), .RAM_CE1n(RAM_CE1n), - .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), + .datain(rd1_dat), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), - .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), + .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy), .debug(debug_extfifo), @@ -701,9 +689,9 @@ module u2_core serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes (.clk(dsp_clk),.rst(dsp_rst), .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), + .rd_dat_i(rd0_dat[31:0]),.rd_flags_i(rd0_dat[35:32]),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), + .wr_dat_o(wr0_dat[31:0]),.wr_flags_o(wr0_dat[35:32]),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); @@ -725,7 +713,7 @@ module u2_core // Debug Pins assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; - assign debug = 32'd0; // debug_extfifo; + assign debug = 32'd0; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 759f7b7b8..bc7ae5f16 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -471,7 +471,7 @@ module u2_rev3 // - u2_core #(.RAM_SIZE(16384), .RAM_AW(14)) + u2_core u2_core(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), diff --git a/usrp2/top/u2_rev3_2rx_iad/Makefile b/usrp2/top/u2_rev3_2rx_iad/Makefile index 5b7ed5a8e..334089839 100644 --- a/usrp2/top/u2_rev3_2rx_iad/Makefile +++ b/usrp2/top/u2_rev3_2rx_iad/Makefile @@ -120,7 +120,6 @@ eth/rtl/verilog/flow_ctrl_tx.v \ eth/rtl/verilog/miim/eth_clockgen.v \ eth/rtl/verilog/miim/eth_outputcontrol.v \ eth/rtl/verilog/miim/eth_shiftreg.v \ -extram/wb_zbt16_b.v \ opencores/8b10b/decode_8b10b.v \ opencores/8b10b/encode_8b10b.v \ opencores/aemb/rtl/verilog/aeMB_bpcu.v \ diff --git a/usrp2/top/u2_rev3_iad/Makefile b/usrp2/top/u2_rev3_iad/Makefile index 5ae8846dd..15df9e43e 100644 --- a/usrp2/top/u2_rev3_iad/Makefile +++ b/usrp2/top/u2_rev3_iad/Makefile @@ -120,7 +120,6 @@ eth/rtl/verilog/flow_ctrl_tx.v \ eth/rtl/verilog/miim/eth_clockgen.v \ eth/rtl/verilog/miim/eth_outputcontrol.v \ eth/rtl/verilog/miim/eth_shiftreg.v \ -extram/wb_zbt16_b.v \ opencores/8b10b/decode_8b10b.v \ opencores/8b10b/encode_8b10b.v \ opencores/aemb/rtl/verilog/aeMB_bpcu.v \ diff --git a/usrp2/top/u2plus/Makefile b/usrp2/top/u2plus/Makefile index c38bd3ec1..38400ce62 100644 --- a/usrp2/top/u2plus/Makefile +++ b/usrp2/top/u2plus/Makefile @@ -23,7 +23,6 @@ include ../../opencores/Makefile.srcs include ../../vrt/Makefile.srcs include ../../udp/Makefile.srcs include ../../coregen/Makefile.srcs -include ../../extram/Makefile.srcs include ../../extramfifo/Makefile.srcs diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v index 3edb539f7..2f9869930 100644 --- a/usrp2/top/u2plus/u2plus_core.v +++ b/usrp2/top/u2plus/u2plus_core.v @@ -131,20 +131,24 @@ module u2plus_core output spiflash_cs, output spiflash_clk, input spiflash_miso, output spiflash_mosi ); - localparam SR_BUF_POOL = 64; // router + localparam SR_MISC = 0; // Uses 9 regs + localparam SR_BUF_POOL = 64; // Uses 4 regs localparam SR_UDP_SM = 96; // 64 regs - localparam SR_RX_DSP = 160; // 16 - localparam SR_RX_CTRL = 176; // 16 + localparam SR_RX_DSP0 = 160; // 16 + localparam SR_RX_CTRL0 = 176; // 16 localparam SR_TIME64 = 192; // 3 localparam SR_SIMTIMER = 198; // 2 localparam SR_TX_DSP = 208; // 16 localparam SR_TX_CTRL = 224; // 16 - + localparam SR_RX_DSP1 = 240; + localparam SR_RX_CTRL1 = 32; + + // FIFO Sizes, 9 = 512 lines, 10 = 1024, 11 = 2048 // all (most?) are 36 bits wide, so 9 is 1 BRAM, 10 is 2, 11 is 4 BRAMs - localparam DSP_TX_FIFOSIZE = 10; - localparam DSP_RX_FIFOSIZE = 10; - localparam ETH_TX_FIFOSIZE = 10; + // localparam DSP_TX_FIFOSIZE = 9; unused -- DSPTX uses extram fifo + localparam DSP_RX_FIFOSIZE = 9; + localparam ETH_TX_FIFOSIZE = 9; localparam ETH_RX_FIFOSIZE = 11; localparam SERDES_TX_FIFOSIZE = 9; localparam SERDES_RX_FIFOSIZE = 9; // RX currently doesn't use a fifo? @@ -153,18 +157,19 @@ module u2plus_core wire [31:0] set_data, set_data_dsp; wire set_stb, set_stb_dsp; - reg wb_rst; wire dsp_rst; - + reg wb_rst; + wire dsp_rst = wb_rst; + wire [31:0] status; wire bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int; - wire proc_int, overrun, underrun; + wire proc_int, overrun0, overrun1, underrun; wire [3:0] uart_tx_int, uart_rx_int; wire [31:0] debug_gpio_0, debug_gpio_1; wire [31:0] atr_lines; wire [31:0] debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc, - debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp; + debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2; wire [15:0] ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2; wire ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2; @@ -174,7 +179,9 @@ module u2plus_core wire epoch; wire [31:0] irq; wire [63:0] vita_time, vita_time_pps; - wire run_rx, run_tx; + + wire run_rx0, run_rx1, run_tx; + reg run_rx0_d1, run_rx1_d1; // /////////////////////////////////////////////////////////////////////////////////////////////// // Wishbone Single Master INTERCON @@ -341,15 +348,13 @@ module u2plus_core wire rd1_ready_i, rd1_ready_o; wire rd2_ready_i, rd2_ready_o; wire rd3_ready_i, rd3_ready_o; - wire [3:0] rd0_flags, rd1_flags, rd2_flags, rd3_flags; - wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; + wire [35:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat; wire wr0_ready_i, wr0_ready_o; wire wr1_ready_i, wr1_ready_o; wire wr2_ready_i, wr2_ready_o; wire wr3_ready_i, wr3_ready_o; - wire [3:0] wr0_flags, wr1_flags, wr2_flags, wr3_flags; - wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; + wire [35:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat; wire [35:0] tx_err_data; wire tx_err_src_rdy, tx_err_dst_rdy; @@ -367,14 +372,15 @@ module u2plus_core .status(status), .sys_int_o(buffer_int), .debug(router_debug), - .ser_inp_data({wr0_flags, wr0_dat}), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), - .dsp_inp_data({wr1_flags, wr1_dat}), .dsp_inp_valid(wr1_ready_i), .dsp_inp_ready(wr1_ready_o), - .eth_inp_data({wr2_flags, wr2_dat}), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), + .ser_inp_data(wr0_dat), .ser_inp_valid(wr0_ready_i), .ser_inp_ready(wr0_ready_o), + .dsp0_inp_data(wr1_dat), .dsp0_inp_valid(wr1_ready_i), .dsp0_inp_ready(wr1_ready_o), + .dsp1_inp_data(wr3_dat), .dsp1_inp_valid(wr3_ready_i), .dsp1_inp_ready(wr3_ready_o), + .eth_inp_data(wr2_dat), .eth_inp_valid(wr2_ready_i), .eth_inp_ready(wr2_ready_o), .err_inp_data(tx_err_data), .err_inp_ready(tx_err_dst_rdy), .err_inp_valid(tx_err_src_rdy), - .ser_out_data({rd0_flags, rd0_dat}), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), - .dsp_out_data({rd1_flags, rd1_dat}), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), - .eth_out_data({rd2_flags, rd2_dat}), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) + .ser_out_data(rd0_dat), .ser_out_valid(rd0_ready_o), .ser_out_ready(rd0_ready_i), + .dsp_out_data(rd1_dat), .dsp_out_valid(rd1_ready_o), .dsp_out_ready(rd1_ready_i), + .eth_out_data(rd2_dat), .eth_out_valid(rd2_ready_o), .eth_out_ready(rd2_ready_i) ); // ///////////////////////////////////////////////////////////////////////// @@ -410,12 +416,12 @@ module u2plus_core // Buffer Pool Status -- Slave #5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = 32'd4; + localparam compat_num = 32'd5; wb_readback_mux buff_pool_status (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb), .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack), - + .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0), .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0), .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]), @@ -426,56 +432,21 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////// // Ethernet MAC Slave #6 - wire [18:0] rx_f19_data, tx_f19_data; - wire rx_f19_src_rdy, rx_f19_dst_rdy, tx_f19_src_rdy, tx_f19_dst_rdy; - - simple_gemac_wrapper19 #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper19 + simple_gemac_wrapper #(.RXFIFOSIZE(ETH_RX_FIFOSIZE), + .TXFIFOSIZE(ETH_TX_FIFOSIZE)) simple_gemac_wrapper19 (.clk125(clk_to_mac), .reset(wb_rst), .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN), .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD), .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV), .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD), .sys_clk(dsp_clk), - .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy), - .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy), + .rx_f36_data(wr2_dat), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o), + .tx_f36_data(rd2_dat), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i), .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(s6_stb), .wb_cyc(s6_cyc), .wb_ack(s6_ack), .wb_we(s6_we), .wb_adr(s6_adr), .wb_dat_i(s6_dat_o), .wb_dat_o(s6_dat_i), .mdio(MDIO), .mdc(MDC), .debug(debug_mac)); - wire [35:0] rx_f36_data, tx_f36_data; - wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; - - wire [18:0] _rx_f19_data; - wire _rx_f19_src_rdy, _rx_f19_dst_rdy; - - //mac rx to eth input... - fifo19_rxrealign fifo19_rxrealign - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy), - .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) ); - - fifo19_to_fifo36 eth_inp_fifo19_to_fifo36 - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy), - .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) ); - - fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(rx_f36_data), .src_rdy_i(rx_f36_src_rdy), .dst_rdy_o(rx_f36_dst_rdy), - .dataout({wr2_flags,wr2_dat}), .src_rdy_o(wr2_ready_i), .dst_rdy_i(wr2_ready_o)); - - //eth output to mac tx... - fifo_cascade #(.WIDTH(36), .SIZE(ETH_TX_FIFOSIZE)) tx_eth_fifo - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain({rd2_flags,rd2_dat}), .src_rdy_i(rd2_ready_o), .dst_rdy_o(rd2_ready_i), - .dataout(tx_f36_data), .src_rdy_o(tx_f36_src_rdy), .dst_rdy_i(tx_f36_dst_rdy)); - - fifo36_to_fifo19 eth_out_fifo36_to_fifo19 - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .f36_datain(tx_f36_data), .f36_src_rdy_i(tx_f36_src_rdy), .f36_dst_rdy_o(tx_f36_dst_rdy), - .f19_dataout(tx_f19_data), .f19_src_rdy_o(tx_f19_src_rdy), .f19_dst_rdy_i(tx_f19_dst_rdy) ); - // ///////////////////////////////////////////////////////////////////////// // Settings Bus -- Slave #7 settings_bus settings_bus @@ -498,15 +469,15 @@ module u2plus_core wire phy_reset; assign PHY_RESETn = ~phy_reset; - setting_reg #(.my_addr(0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), + setting_reg #(.my_addr(SR_MISC+0),.width(8)) sr_clk (.clk(wb_clk),.rst(wb_rst),.strobe(s7_ack),.addr(set_addr), .in(set_data),.out(clock_outs),.changed()); - setting_reg #(.my_addr(1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(SR_MISC+1),.width(8)) sr_ser (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(serdes_outs),.changed()); - setting_reg #(.my_addr(2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(SR_MISC+2),.width(8)) sr_adc (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(adc_outs),.changed()); - setting_reg #(.my_addr(4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(SR_MISC+4),.width(1)) sr_phy (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phy_reset),.changed()); - setting_reg #(.my_addr(5),.width(1)) sr_bldr (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(SR_MISC+5),.width(1)) sr_bldr (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(bldr_done),.changed()); // ///////////////////////////////////////////////////////////////////////// @@ -516,12 +487,12 @@ module u2plus_core // In Rev3 there are only 6 leds, and the highest one is on the ETH connector wire [7:0] led_src, led_sw; - wire [7:0] led_hw = {run_tx, run_rx, clk_status, serdes_link_up, 1'b0}; + wire [7:0] led_hw = {run_tx, (run_rx0_d1 | run_rx1_d1), clk_status, serdes_link_up, 1'b0}; - setting_reg #(.my_addr(3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), + setting_reg #(.my_addr(SR_MISC+3),.width(8)) sr_led (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_sw),.changed()); - setting_reg #(.my_addr(8),.width(8), .at_reset(8'b0001_1110)) + setting_reg #(.my_addr(SR_MISC+8),.width(8), .at_reset(8'b0001_1110)) sr_led_src (.clk(wb_clk),.rst(wb_rst), .strobe(set_stb),.addr(set_addr), .in(set_data),.out(led_src),.changed()); assign leds = (led_src & led_hw) | (~led_src & led_sw); @@ -533,7 +504,7 @@ module u2plus_core wire underrun_wb, overrun_wb, pps_wb; oneshot_2clk underrun_1s (.clk_in(dsp_clk), .in(underrun), .clk_out(wb_clk), .out(underrun_wb)); - oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun), .clk_out(wb_clk), .out(overrun_wb)); + oneshot_2clk overrun_1s (.clk_in(dsp_clk), .in(overrun0 | overrun1), .clk_out(wb_clk), .out(overrun_wb)); oneshot_2clk pps_1s (.clk_in(dsp_clk), .in(pps_int), .clk_out(wb_clk), .out(pps_wb)); assign irq= {{8'b0}, @@ -572,15 +543,11 @@ module u2plus_core // ///////////////////////////////////////////////////////////////////////// // ATR Controller, Slave #11 - reg run_rx_d1; - always @(posedge dsp_clk) - run_rx_d1 <= run_rx; - atr_controller atr_controller (.clk_i(wb_clk),.rst_i(wb_rst), .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack), - .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); + .run_rx(run_rx0_d1 | run_rx1_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) ); // ////////////////////////////////////////////////////////////////////////// // Time Sync, Slave #12 @@ -605,50 +572,72 @@ module u2plus_core .sclk_pad_o(spiflash_clk),.mosi_pad_o(spiflash_mosi),.miso_pad_i(spiflash_miso) ); // ///////////////////////////////////////////////////////////////////////// - // DSP RX - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy; - wire [99:0] rx_data; - wire [35:0] rx1_data; + // DSP RX 0 + wire [31:0] sample_rx0; + wire [35:0] rx0_data; + wire clear_rx0, strobe_rx0, rx0_dst_rdy, rx0_src_rdy; + + always @(posedge dsp_clk) + run_rx0_d1 <= run_rx0; - dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx + dsp_core_rx #(.BASE(SR_RX_DSP0)) dsp_core_rx0 (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), - .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx), - .debug(debug_rx_dsp) ); + .sample(sample_rx0), .run(run_rx0_d1), .strobe(strobe_rx0), + .debug() ); - wire [31:0] vrc_debug; - wire clear_rx; - - setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear + setting_reg #(.my_addr(SR_RX_CTRL0+3)) sr_clear_rx0 (.clk(dsp_clk),.rst(dsp_rst), .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), - .out(),.changed(clear_rx)); + .out(),.changed(clear_rx0)); - vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + vita_rx_chain #(.BASE(SR_RX_CTRL0)) vita_rx_chain0 + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .vita_time(vita_time), .overrun(overrun), - .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .sample_fifo_o(rx_data), .sample_fifo_dst_rdy_i(rx_dst_rdy), .sample_fifo_src_rdy_o(rx_src_rdy), - .debug_rx(vrc_debug)); + .vita_time(vita_time), .overrun(overrun0), + .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), + .rx_data_o(rx0_data), .rx_src_rdy_o(rx0_src_rdy), .rx_dst_rdy_i(rx0_dst_rdy), + .debug() ); + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade0 + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx0), + .datain(rx0_data), .src_rdy_i(rx0_src_rdy), .dst_rdy_o(rx0_dst_rdy), + .dataout(wr1_dat), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); + + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 1 + wire [31:0] sample_rx1; + wire [35:0] rx1_data; + wire clear_rx1, strobe_rx1, rx1_dst_rdy, rx1_src_rdy; - wire [3:0] vita_state; + always @(posedge dsp_clk) + run_rx1_d1 <= run_rx1; - vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 + (.clk(dsp_clk),.rst(dsp_rst), .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), - .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy), - .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy), - .fifo_occupied(), .fifo_full(), .fifo_empty(), - .debug_rx(vita_state) ); + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), + .debug() ); - fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade - (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx), + setting_reg #(.my_addr(SR_RX_CTRL1+3)) sr_clear_rx1 + (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx1)); + + vita_rx_chain #(.BASE(SR_RX_CTRL1)) vita_rx_chain1 + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), .overrun(overrun1), + .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), + .rx_data_o(rx1_data), .rx_src_rdy_o(rx1_src_rdy), .rx_dst_rdy_i(rx1_dst_rdy), + .debug() ); + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade1 + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), - .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); + .dataout(wr3_dat), .src_rdy_o(wr3_ready_i), .dst_rdy_i(wr3_ready_o)); // /////////////////////////////////////////////////////////////////////////////////// // DSP TX @@ -678,10 +667,10 @@ module u2plus_core .RAM_LDn(RAM_LDn), .RAM_OEn(RAM_OEn), .RAM_CE1n(RAM_CE1n), - .datain({rd1_flags[3:2],rd1_dat[31:16],rd1_flags[1:0],rd1_dat[15:0]}), + .datain(rd1_dat), .src_rdy_i(rd1_ready_o), .dst_rdy_o(rd1_ready_i), - .dataout({tx_data[35:34],tx_data[31:16],tx_data[33:32],tx_data[15:0]}), + .dataout(tx_data), .src_rdy_o(tx_src_rdy), .dst_rdy_i(tx_dst_rdy), .debug(debug_extfifo), @@ -701,17 +690,15 @@ module u2plus_core .underrun(underrun), .run(run_tx), .debug(debug_vt)); - assign dsp_rst = wb_rst; - // /////////////////////////////////////////////////////////////////////////////////// // SERDES serdes #(.TXFIFOSIZE(SERDES_TX_FIFOSIZE),.RXFIFOSIZE(SERDES_RX_FIFOSIZE)) serdes (.clk(dsp_clk),.rst(dsp_rst), .ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb), - .rd_dat_i(rd0_dat),.rd_flags_i(rd0_flags),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), + .rd_dat_i(rd0_dat[31:0]),.rd_flags_i(rd0_dat[35:32]),.rd_ready_o(rd0_ready_i),.rd_ready_i(rd0_ready_o), .ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb), - .wr_dat_o(wr0_dat),.wr_flags_o(wr0_flags),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), + .wr_dat_o(wr0_dat[31:0]),.wr_flags_o(wr0_dat[35:32]),.wr_ready_o(wr0_ready_i),.wr_ready_i(wr0_ready_o), .tx_occupied(ser_tx_occ),.tx_full(ser_tx_full),.tx_empty(ser_tx_empty), .rx_occupied(ser_rx_occ),.rx_full(ser_rx_full),.rx_empty(ser_rx_empty), .serdes_link_up(serdes_link_up),.debug0(debug_serdes0), .debug1(debug_serdes1) ); @@ -720,18 +707,18 @@ module u2plus_core // VITA Timing wire [31:0] debug_sync; - + time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp), .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), .exp_time_in(exp_time_in), .exp_time_out(exp_time_out), .debug(debug_sync)); - + // ///////////////////////////////////////////////////////////////////////////////////////// // Debug Pins assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac}; - assign debug = 32'd0; // debug_extfifo; + assign debug = 32'd0; assign debug_gpio_0 = 32'd0; assign debug_gpio_1 = 32'd0; diff --git a/usrp2/vrt/Makefile.srcs b/usrp2/vrt/Makefile.srcs index aa1356d82..4851bc924 100644 --- a/usrp2/vrt/Makefile.srcs +++ b/usrp2/vrt/Makefile.srcs @@ -8,6 +8,7 @@ VRT_SRCS = $(abspath $(addprefix $(BASE_DIR)/../vrt/, \ vita_rx_control.v \ vita_rx_framer.v \ +vita_rx_chain.v \ vita_tx_control.v \ vita_tx_deframer.v \ vita_tx_chain.v \ diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v new file mode 100644 index 000000000..f5578eb15 --- /dev/null +++ b/usrp2/vrt/vita_rx_chain.v @@ -0,0 +1,33 @@ + +module vita_rx_chain + #(parameter BASE=0) + (input clk, input reset, input clear, + input set_stb, input [7:0] set_addr, input [31:0] set_data, + input [63:0] vita_time, output overrun, + input [31:0] sample, output run, input strobe, + output [35:0] rx_data_o, output rx_src_rdy_o, input rx_dst_rdy_i, + output [31:0] debug ); + + wire [100:0] sample_data; + wire sample_dst_rdy, sample_src_rdy; + wire [31:0] vrc_debug, vrf_debug; + + vita_rx_control #(.BASE(BASE), .WIDTH(32)) vita_rx_control + (.clk(clk), .reset(reset), .clear(clear), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .vita_time(vita_time), .overrun(overrun), + .sample(sample), .run(run), .strobe(strobe), + .sample_fifo_o(sample_data), .sample_fifo_dst_rdy_i(sample_dst_rdy), .sample_fifo_src_rdy_o(sample_src_rdy), + .debug_rx(vrc_debug)); + + vita_rx_framer #(.BASE(BASE), .MAXCHAN(1)) vita_rx_framer + (.clk(clk), .reset(reset), .clear(clear), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .sample_fifo_i(sample_data), .sample_fifo_dst_rdy_o(sample_dst_rdy), .sample_fifo_src_rdy_i(sample_src_rdy), + .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i), + .fifo_occupied(), .fifo_full(), .fifo_empty(), + .debug_rx(vrf_debug) ); + + assign debug = vrc_debug; // | vrf_debug; + +endmodule // vita_rx_chain |