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-rw-r--r--host/lib/usrp/usrp2/dsp_impl.cpp6
-rw-r--r--host/lib/usrp/usrp2/mboard_impl.cpp39
-rw-r--r--host/lib/usrp/usrp2/usrp2_impl.cpp28
-rw-r--r--host/lib/usrp/usrp2/usrp2_impl.hpp2
-rw-r--r--host/lib/usrp/usrp2/usrp2_regs.cpp45
-rw-r--r--host/lib/usrp/usrp2/usrp2_regs.hpp34
6 files changed, 89 insertions, 65 deletions
diff --git a/host/lib/usrp/usrp2/dsp_impl.cpp b/host/lib/usrp/usrp2/dsp_impl.cpp
index ec3e6082c..c83565875 100644
--- a/host/lib/usrp/usrp2/dsp_impl.cpp
+++ b/host/lib/usrp/usrp2/dsp_impl.cpp
@@ -98,7 +98,7 @@ void usrp2_mboard_impl::ddc_set(const wax::obj &key_, const wax::obj &val){
case DSP_PROP_FREQ_SHIFT:{
double new_freq = val.as<double>();
- _iface->poke32(_iface->regs.dsp0_rx_freq,
+ _iface->poke32(_iface->regs.dsp_rx[0].freq,
dsp_type1::calc_cordic_word_and_update(new_freq, get_master_clock_freq())
);
_ddc_freq = new_freq; //shadow
@@ -110,11 +110,11 @@ void usrp2_mboard_impl::ddc_set(const wax::obj &key_, const wax::obj &val){
_ddc_decim = pick_closest_rate(extact_rate, _allowed_decim_and_interp_rates);
//set the decimation
- _iface->poke32(_iface->regs.dsp0_rx_decim_rate, dsp_type1::calc_cic_filter_word(_ddc_decim));
+ _iface->poke32(_iface->regs.dsp_rx[0].decim_rate, dsp_type1::calc_cic_filter_word(_ddc_decim));
//set the scaling
static const boost::int16_t default_rx_scale_iq = 1024;
- _iface->poke32(_iface->regs.dsp0_rx_scale_iq,
+ _iface->poke32(_iface->regs.dsp_rx[0].scale_iq,
dsp_type1::calc_iq_scale_word(default_rx_scale_iq, default_rx_scale_iq)
);
}
diff --git a/host/lib/usrp/usrp2/mboard_impl.cpp b/host/lib/usrp/usrp2/mboard_impl.cpp
index 5f3537f1e..a3de8673e 100644
--- a/host/lib/usrp/usrp2/mboard_impl.cpp
+++ b/host/lib/usrp/usrp2/mboard_impl.cpp
@@ -22,7 +22,6 @@
#include <uhd/usrp/dsp_utils.hpp>
#include <uhd/usrp/mboard_props.hpp>
#include <uhd/utils/assert.hpp>
-#include <uhd/utils/byteswap.hpp>
#include <uhd/utils/algorithm.hpp>
#include <boost/bind.hpp>
#include <iostream>
@@ -48,21 +47,6 @@ usrp2_mboard_impl::usrp2_mboard_impl(
_index(index),
_iface(usrp2_iface::make(ctrl_transport))
{
- //Send a small data packet so the usrp2 knows the udp source port.
- //This setup must happen before further initialization occurs
- //or the async update packets will cause ICMP destination unreachable.
- transport::managed_send_buffer::sptr send_buff;
- static const boost::uint32_t data[2] = {
- uhd::htonx(boost::uint32_t(0 /* don't care seq num */)),
- uhd::htonx(boost::uint32_t(USRP2_INVALID_VRT_HEADER))
- };
- send_buff = data_transport->get_send_buff();
- std::memcpy(send_buff->cast<void*>(), &data, sizeof(data));
- send_buff->commit(sizeof(data));
- send_buff = err0_transport->get_send_buff();
- std::memcpy(send_buff->cast<void*>(), &data, sizeof(data));
- send_buff->commit(sizeof(data));
-
//contruct the interfaces to mboard perifs
_clock_ctrl = usrp2_clock_ctrl::make(_iface);
_codec_ctrl = usrp2_codec_ctrl::make(_iface);
@@ -87,17 +71,18 @@ usrp2_mboard_impl::usrp2_mboard_impl(
}
//setup the vrt rx registers
- _iface->poke32(_iface->regs.rx_ctrl0_clear_overrun, 1); //reset
- _iface->poke32(_iface->regs.rx_ctrl0_nsamps_per_pkt, recv_samps_per_packet);
- _iface->poke32(_iface->regs.rx_ctrl0_nchannels, 1);
- _iface->poke32(_iface->regs.rx_ctrl0_vrt_header, 0
+ //TODO loop for 0, 1, in NUM_RX_DSPS
+ _iface->poke32(_iface->regs.rx_ctrl[0].clear_overrun, 1); //reset
+ _iface->poke32(_iface->regs.rx_ctrl[0].nsamps_per_pkt, recv_samps_per_packet);
+ _iface->poke32(_iface->regs.rx_ctrl[0].nchannels, 1);
+ _iface->poke32(_iface->regs.rx_ctrl[0].vrt_header, 0
| (0x1 << 28) //if data with stream id
| (0x1 << 26) //has trailer
| (0x3 << 22) //integer time other
| (0x1 << 20) //fractional time sample count
);
- _iface->poke32(_iface->regs.rx_ctrl0_vrt_stream_id, usrp2_impl::RECV_SID);
- _iface->poke32(_iface->regs.rx_ctrl0_vrt_trailer, 0);
+ _iface->poke32(_iface->regs.rx_ctrl[0].vrt_stream_id, usrp2_impl::RECV_SID);
+ _iface->poke32(_iface->regs.rx_ctrl[0].vrt_trailer, 0);
_iface->poke32(_iface->regs.time64_tps, size_t(get_master_clock_freq()));
//init the tx control registers
@@ -164,7 +149,7 @@ usrp2_mboard_impl::usrp2_mboard_impl(
this->issue_ddc_stream_cmd(stream_cmd);
data_transport->get_recv_buff().get(); //recv with timeout for lingering
data_transport->get_recv_buff().get(); //recv with timeout for expected
- _iface->poke32(_iface->regs.rx_ctrl0_clear_overrun, 1); //resets sequence
+ _iface->poke32(_iface->regs.rx_ctrl[0].clear_overrun, 1); //resets sequence
}
usrp2_mboard_impl::~usrp2_mboard_impl(void){
@@ -273,9 +258,9 @@ void usrp2_mboard_impl::handle_overflow(void){
void usrp2_mboard_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd){
_continuous_streaming = stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS;
- _iface->poke32(_iface->regs.rx_ctrl0_stream_cmd, dsp_type1::calc_stream_cmd_word(stream_cmd));
- _iface->poke32(_iface->regs.rx_ctrl0_time_secs, boost::uint32_t(stream_cmd.time_spec.get_full_secs()));
- _iface->poke32(_iface->regs.rx_ctrl0_time_ticks, stream_cmd.time_spec.get_tick_count(get_master_clock_freq()));
+ _iface->poke32(_iface->regs.rx_ctrl[0].stream_cmd, dsp_type1::calc_stream_cmd_word(stream_cmd));
+ _iface->poke32(_iface->regs.rx_ctrl[0].time_secs, boost::uint32_t(stream_cmd.time_spec.get_full_secs()));
+ _iface->poke32(_iface->regs.rx_ctrl[0].time_ticks, stream_cmd.time_spec.get_tick_count(get_master_clock_freq()));
}
/***********************************************************************
@@ -397,7 +382,7 @@ void usrp2_mboard_impl::set(const wax::obj &key, const wax::obj &val){
//sanity check
UHD_ASSERT_THROW(_rx_subdev_spec.size() <= 2);
//set the mux
- if (_rx_subdev_spec.size() >= 1) _iface->poke32(_iface->regs.dsp0_rx_mux, dsp_type1::calc_rx_mux_word(
+ if (_rx_subdev_spec.size() >= 1) _iface->poke32(_iface->regs.dsp_rx[0].mux, dsp_type1::calc_rx_mux_word(
_dboard_manager->get_rx_subdev(_rx_subdev_spec[0].sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>()
));
//TODO
diff --git a/host/lib/usrp/usrp2/usrp2_impl.cpp b/host/lib/usrp/usrp2/usrp2_impl.cpp
index d40a96364..78eda4f62 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.cpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.cpp
@@ -22,6 +22,7 @@
#include <uhd/utils/assert.hpp>
#include <uhd/utils/static.hpp>
#include <uhd/utils/warning.hpp>
+#include <uhd/utils/byteswap.hpp>
#include <boost/algorithm/string.hpp> //for split
#include <boost/assign/list_of.hpp>
#include <boost/format.hpp>
@@ -29,7 +30,7 @@
#include <boost/lexical_cast.hpp>
#include <boost/regex.hpp>
#include <boost/bind.hpp>
-#include <boost/asio.hpp> //htonl and ntohl
+#include <boost/asio/ip/address_v4.hpp>
#include <iostream>
#include <vector>
@@ -147,8 +148,8 @@ static device_addrs_t usrp2_find(const device_addr_t &hint_){
//send a hello control packet
usrp2_ctrl_data_t ctrl_data_out;
- ctrl_data_out.proto_ver = htonl(USRP2_FW_COMPAT_NUM);
- ctrl_data_out.id = htonl(USRP2_CTRL_ID_WAZZUP_BRO);
+ ctrl_data_out.proto_ver = uhd::htonx<boost::uint32_t>(USRP2_FW_COMPAT_NUM);
+ ctrl_data_out.id = uhd::htonx<boost::uint32_t>(USRP2_CTRL_ID_WAZZUP_BRO);
udp_transport->send(boost::asio::buffer(&ctrl_data_out, sizeof(ctrl_data_out)));
//loop and recieve until the timeout
@@ -157,9 +158,9 @@ static device_addrs_t usrp2_find(const device_addr_t &hint_){
while(true){
size_t len = udp_transport->recv(asio::buffer(usrp2_ctrl_data_in_mem));
//std::cout << len << "\n";
- if (len > offsetof(usrp2_ctrl_data_t, data) and ntohl(ctrl_data_in->id) == USRP2_CTRL_ID_WAZZUP_DUDE){
+ if (len > offsetof(usrp2_ctrl_data_t, data) and uhd::ntohx(ctrl_data_in->id) == USRP2_CTRL_ID_WAZZUP_DUDE){
//make a boost asio ipv4 with the raw addr in host byte order
- boost::asio::ip::address_v4 ip_addr(ntohl(ctrl_data_in->data.ip_addr));
+ boost::asio::ip::address_v4 ip_addr(uhd::ntohx(ctrl_data_in->data.ip_addr));
device_addr_t new_addr;
new_addr["type"] = "usrp2";
new_addr["addr"] = ip_addr.to_string();
@@ -215,16 +216,33 @@ static device::sptr usrp2_make(const device_addr_t &device_addr){
std::vector<zero_copy_if::sptr> err0_transports;
const device_addrs_t device_addrs = sep_indexed_dev_addrs(device_addr);
+ //Send a small data packet so the usrp2 knows the udp source port.
+ //This setup must happen before further initialization occurs
+ //or the async update packets will cause ICMP destination unreachable.
+ transport::managed_send_buffer::sptr send_buff;
+ static const boost::uint32_t data[2] = {
+ uhd::htonx(boost::uint32_t(0 /* don't care seq num */)),
+ uhd::htonx(boost::uint32_t(USRP2_INVALID_VRT_HEADER))
+ };
+
BOOST_FOREACH(const device_addr_t &dev_addr_i, device_addrs){
ctrl_transports.push_back(udp_simple::make_connected(
dev_addr_i["addr"], num2str(USRP2_UDP_CTRL_PORT)
));
+
data_transports.push_back(udp_zero_copy::make(
dev_addr_i["addr"], num2str(USRP2_UDP_DSP0_PORT), dsp_xport_hints
));
+ send_buff = data_transports.back()->get_send_buff();
+ std::memcpy(send_buff->cast<void*>(), &data, sizeof(data));
+ send_buff->commit(sizeof(data));
+
err0_transports.push_back(udp_zero_copy::make(
dev_addr_i["addr"], num2str(USRP2_UDP_ERR0_PORT), device_addr_t()
));
+ send_buff = err0_transports.back()->get_send_buff();
+ std::memcpy(send_buff->cast<void*>(), &data, sizeof(data));
+ send_buff->commit(sizeof(data));
}
//create the usrp2 implementation guts
diff --git a/host/lib/usrp/usrp2/usrp2_impl.hpp b/host/lib/usrp/usrp2/usrp2_impl.hpp
index 337f842d6..9a406bc87 100644
--- a/host/lib/usrp/usrp2/usrp2_impl.hpp
+++ b/host/lib/usrp/usrp2/usrp2_impl.hpp
@@ -181,6 +181,8 @@ public:
static const size_t sram_bytes = size_t(1 << 20);
static const boost::uint32_t RECV_SID = 1;
static const boost::uint32_t ASYNC_SID = 2;
+ static const size_t NUM_RX_DSPS = 2;
+ static const size_t NUM_TX_DSPS = 1;
/*!
* Create a new usrp2 impl base.
diff --git a/host/lib/usrp/usrp2/usrp2_regs.cpp b/host/lib/usrp/usrp2/usrp2_regs.cpp
index 2159c4276..31c904960 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.cpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.cpp
@@ -70,12 +70,18 @@ usrp2_regs_t usrp2_get_regs(bool use_n2xx_map) {
x.dsp_tx_scale_iq = sr_addr(misc_output_base, x.sr_tx_dsp + 1);
x.dsp_tx_interp_rate = sr_addr(misc_output_base, x.sr_tx_dsp + 2);
x.dsp_tx_mux = sr_addr(misc_output_base, x.sr_tx_dsp + 4);
- x.dsp0_rx_freq = sr_addr(misc_output_base, x.sr_rx_dsp0 + 0);
- x.dsp0_rx_scale_iq = sr_addr(misc_output_base, x.sr_rx_dsp0 + 1);
- x.dsp0_rx_decim_rate = sr_addr(misc_output_base, x.sr_rx_dsp0 + 2);
- x.dsp0_rx_dcoffset_i = sr_addr(misc_output_base, x.sr_rx_dsp0 + 3);
- x.dsp0_rx_dcoffset_q = sr_addr(misc_output_base, x.sr_rx_dsp0 + 4);
- x.dsp0_rx_mux = sr_addr(misc_output_base, x.sr_rx_dsp0 + 5);
+ x.dsp_rx[0].freq = sr_addr(misc_output_base, x.sr_rx_dsp0 + 0);
+ x.dsp_rx[0].scale_iq = sr_addr(misc_output_base, x.sr_rx_dsp0 + 1);
+ x.dsp_rx[0].decim_rate = sr_addr(misc_output_base, x.sr_rx_dsp0 + 2);
+ x.dsp_rx[0].dcoffset_i = sr_addr(misc_output_base, x.sr_rx_dsp0 + 3);
+ x.dsp_rx[0].dcoffset_q = sr_addr(misc_output_base, x.sr_rx_dsp0 + 4);
+ x.dsp_rx[0].mux = sr_addr(misc_output_base, x.sr_rx_dsp0 + 5);
+ x.dsp_rx[1].freq = sr_addr(misc_output_base, x.sr_rx_dsp1 + 1);
+ x.dsp_rx[1].scale_iq = sr_addr(misc_output_base, x.sr_rx_dsp1 + 1);
+ x.dsp_rx[1].decim_rate = sr_addr(misc_output_base, x.sr_rx_dsp1 + 2);
+ x.dsp_rx[1].dcoffset_i = sr_addr(misc_output_base, x.sr_rx_dsp1 + 3);
+ x.dsp_rx[1].dcoffset_q = sr_addr(misc_output_base, x.sr_rx_dsp1 + 4);
+ x.dsp_rx[1].mux = sr_addr(misc_output_base, x.sr_rx_dsp1 + 5);
x.gpio_io = gpio_base + 0;
x.gpio_ddr = gpio_base + 4;
x.gpio_tx_sel = gpio_base + 8;
@@ -88,15 +94,24 @@ usrp2_regs_t usrp2_get_regs(bool use_n2xx_map) {
x.atr_inrx_rxside = atr_base + 10;
x.atr_full_txside = atr_base + 12;
x.atr_full_rxside = atr_base + 14;
- x.rx_ctrl0_stream_cmd = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 0);
- x.rx_ctrl0_time_secs = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 1);
- x.rx_ctrl0_time_ticks = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 2);
- x.rx_ctrl0_clear_overrun = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 3);
- x.rx_ctrl0_vrt_header = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 4);
- x.rx_ctrl0_vrt_stream_id = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 5);
- x.rx_ctrl0_vrt_trailer = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 6);
- x.rx_ctrl0_nsamps_per_pkt = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 7);
- x.rx_ctrl0_nchannels = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 8);
+ x.rx_ctrl[0].stream_cmd = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 0);
+ x.rx_ctrl[0].time_secs = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 1);
+ x.rx_ctrl[0].time_ticks = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 2);
+ x.rx_ctrl[0].clear_overrun = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 3);
+ x.rx_ctrl[0].vrt_header = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 4);
+ x.rx_ctrl[0].vrt_stream_id = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 5);
+ x.rx_ctrl[0].vrt_trailer = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 6);
+ x.rx_ctrl[0].nsamps_per_pkt = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 7);
+ x.rx_ctrl[0].nchannels = sr_addr(misc_output_base, x.sr_rx_ctrl0 + 8);
+ x.rx_ctrl[1].stream_cmd = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 1);
+ x.rx_ctrl[1].time_secs = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 1);
+ x.rx_ctrl[1].time_ticks = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 2);
+ x.rx_ctrl[1].clear_overrun = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 3);
+ x.rx_ctrl[1].vrt_header = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 4);
+ x.rx_ctrl[1].vrt_stream_id = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 5);
+ x.rx_ctrl[1].vrt_trailer = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 6);
+ x.rx_ctrl[1].nsamps_per_pkt = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 7);
+ x.rx_ctrl[1].nchannels = sr_addr(misc_output_base, x.sr_rx_ctrl1 + 8);
x.tx_ctrl_num_chan = sr_addr(misc_output_base, x.sr_tx_ctrl + 0);
x.tx_ctrl_clear_state = sr_addr(misc_output_base, x.sr_tx_ctrl + 1);
x.tx_ctrl_report_sid = sr_addr(misc_output_base, x.sr_tx_ctrl + 2);
diff --git a/host/lib/usrp/usrp2/usrp2_regs.hpp b/host/lib/usrp/usrp2/usrp2_regs.hpp
index e150528a7..01f5ee65a 100644
--- a/host/lib/usrp/usrp2/usrp2_regs.hpp
+++ b/host/lib/usrp/usrp2/usrp2_regs.hpp
@@ -70,12 +70,14 @@ typedef struct {
int dsp_tx_scale_iq;
int dsp_tx_interp_rate;
int dsp_tx_mux;
- int dsp0_rx_freq;
- int dsp0_rx_scale_iq;
- int dsp0_rx_decim_rate;
- int dsp0_rx_dcoffset_i;
- int dsp0_rx_dcoffset_q;
- int dsp0_rx_mux;
+ struct{
+ int freq;
+ int scale_iq;
+ int decim_rate;
+ int dcoffset_i;
+ int dcoffset_q;
+ int mux;
+ } dsp_rx[2];
int gpio_base;
int gpio_io;
int gpio_ddr;
@@ -90,15 +92,17 @@ typedef struct {
int atr_inrx_rxside;
int atr_full_txside;
int atr_full_rxside;
- int rx_ctrl0_stream_cmd;
- int rx_ctrl0_time_secs;
- int rx_ctrl0_time_ticks;
- int rx_ctrl0_clear_overrun;
- int rx_ctrl0_vrt_header;
- int rx_ctrl0_vrt_stream_id;
- int rx_ctrl0_vrt_trailer;
- int rx_ctrl0_nsamps_per_pkt;
- int rx_ctrl0_nchannels;
+ struct{
+ int stream_cmd;
+ int time_secs;
+ int time_ticks;
+ int clear_overrun;
+ int vrt_header;
+ int vrt_stream_id;
+ int vrt_trailer;
+ int nsamps_per_pkt;
+ int nchannels;
+ } rx_ctrl[2];
int tx_ctrl_num_chan;
int tx_ctrl_clear_state;
int tx_ctrl_report_sid;
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-31 20:02:55 +0000